svn commit: r295073 - in head/sys/arm: arm include

[Michal Meloun]

Author: mmel
Date: Sat Jan 30 13:11:13 2016
New Revision: 295073
URL: https://svnweb.freebsd.org/changeset/base/295073

Log:
  ARM: Remove TLB IPI.
  We don't support SMP on ARMv6. All ARMv7 multicore cpus already uses
  hardware broadcast for TLB and cache operations.

Modified:
  head/sys/arm/arm/mp_machdep.c
  head/sys/arm/include/cpufunc.h
  head/sys/arm/include/smp.h

Modified: head/sys/arm/arm/mp_machdep.c
==============================================================================
--- head/sys/arm/arm/mp_machdep.c	Sat Jan 30 12:58:38 2016	(r295072)
+++ head/sys/arm/arm/mp_machdep.c	Sat Jan 30 13:11:13 2016	(r295073)
@@ -341,13 +341,6 @@ ipi_hardclock(void *arg)
 	critical_exit();
 }
 
-static void
-ipi_tlb(void *dummy __unused)
-{
-
-	CTR1(KTR_SMP, "%s: IPI_TLB", __func__);
-	cpufuncs.cf_tlb_flushID();
-}
 #else
 static int
 ipi_handler(void *arg)
@@ -413,10 +406,6 @@ ipi_handler(void *arg)
 			CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
 			hardclockintr();
 			break;
-		case IPI_TLB:
-			CTR1(KTR_SMP, "%s: IPI_TLB", __func__);
-			cpufuncs.cf_tlb_flushID();
-			break;
 		default:
 			panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu);
 		}
@@ -446,7 +435,6 @@ release_aps(void *dummy __unused)
 	intr_ipi_set_handler(IPI_STOP, "stop", ipi_stop, NULL, 0);
 	intr_ipi_set_handler(IPI_PREEMPT, "preempt", ipi_preempt, NULL, 0);
 	intr_ipi_set_handler(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL, 0);
-	intr_ipi_set_handler(IPI_TLB, "tlb", ipi_tlb, NULL, 0);
 
 #else
 #ifdef IPI_IRQ_START
@@ -538,10 +526,3 @@ ipi_selected(cpuset_t cpus, u_int ipi)
 	platform_ipi_send(cpus, ipi);
 }
 
-void
-tlb_broadcast(int ipi)
-{
-
-	if (smp_started)
-		ipi_all_but_self(ipi);
-}

Modified: head/sys/arm/include/cpufunc.h
==============================================================================
--- head/sys/arm/include/cpufunc.h	Sat Jan 30 12:58:38 2016	(r295072)
+++ head/sys/arm/include/cpufunc.h	Sat Jan 30 13:11:13 2016	(r295073)
@@ -184,8 +184,6 @@ extern u_int cputype;
 #define cpu_faultstatus()	cpufuncs.cf_faultstatus()
 #define cpu_faultaddress()	cpufuncs.cf_faultaddress()
 
-#ifndef SMP
-
 #define	cpu_tlb_flushID()	cpufuncs.cf_tlb_flushID()
 #define	cpu_tlb_flushID_SE(e)	cpufuncs.cf_tlb_flushID_SE(e)
 #define	cpu_tlb_flushI()	cpufuncs.cf_tlb_flushI()
@@ -193,51 +191,6 @@ extern u_int cputype;
 #define	cpu_tlb_flushD()	cpufuncs.cf_tlb_flushD()
 #define	cpu_tlb_flushD_SE(e)	cpufuncs.cf_tlb_flushD_SE(e)
 
-#else
-void tlb_broadcast(int);
-
-#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
-#define TLB_BROADCAST	/* No need to explicitely send an IPI */
-#else
-#define TLB_BROADCAST	tlb_broadcast(7)
-#endif
-
-#define	cpu_tlb_flushID() do { \
-	cpufuncs.cf_tlb_flushID(); \
-	TLB_BROADCAST; \
-} while(0)
-
-#define	cpu_tlb_flushID_SE(e) do { \
-	cpufuncs.cf_tlb_flushID_SE(e); \
-	TLB_BROADCAST; \
-} while(0)
-
-
-#define	cpu_tlb_flushI() do { \
-	cpufuncs.cf_tlb_flushI(); \
-	TLB_BROADCAST; \
-} while(0)
-
-
-#define	cpu_tlb_flushI_SE(e) do { \
-	cpufuncs.cf_tlb_flushI_SE(e); \
-	TLB_BROADCAST; \
-} while(0)
-
-
-#define	cpu_tlb_flushD() do { \
-	cpufuncs.cf_tlb_flushD(); \
-	TLB_BROADCAST; \
-} while(0)
-
-
-#define	cpu_tlb_flushD_SE(e) do { \
-	cpufuncs.cf_tlb_flushD_SE(e); \
-	TLB_BROADCAST; \
-} while(0)
-
-#endif
-
 #define	cpu_icache_sync_all()	cpufuncs.cf_icache_sync_all()
 #define	cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
 

Modified: head/sys/arm/include/smp.h
==============================================================================
--- head/sys/arm/include/smp.h	Sat Jan 30 12:58:38 2016	(r295072)
+++ head/sys/arm/include/smp.h	Sat Jan 30 13:11:13 2016	(r295073)
@@ -14,8 +14,8 @@ enum {
 	IPI_STOP,
 	IPI_STOP_HARD = IPI_STOP, /* These are synonyms on arm. */
 	IPI_HARDCLOCK,
-	IPI_TLB,
-	IPI_CACHE,
+	IPI_TLB,		/* Not used now, but keep it reserved. */
+	IPI_CACHE,		/* Not used now, but keep it reserved. */
 	INTR_IPI_COUNT
 };
 #else
@@ -25,8 +25,8 @@ enum {
 #define IPI_STOP	4
 #define IPI_STOP_HARD	4
 #define IPI_HARDCLOCK	6
-#define IPI_TLB		7
-#define IPI_CACHE	8
+#define IPI_TLB		7	/* Not used now, but keep it reserved. */
+#define IPI_CACHE	8	/* Not used now, but keep it reserved. */
 #endif /* INTRNG */
 
 void	init_secondary(int cpu);