svn commit: r285626 - in head/sys/arm64: arm64 include

[Zbigniew Bodek]

Author: zbb
Date: Thu Jul 16 10:22:57 2015
New Revision: 285626
URL: https://svnweb.freebsd.org/changeset/base/285626

Log:
  Set-up proper TCR values for memory related to Translation Table Walking
  
  This commit adds proper cache and shareability attributes to
  the TCR register.
  Set memory attributes to Normal, outer and inner cacheable WBWA.
  Set shareability to inner and outer shareable when SMP is enabled.
  
  Reviewed by:   andrew
  Obtained from: Semihalf
  Sponsored by:  The FreeBSD Foundation
  Differential Revision: https://reviews.freebsd.org/D3093

Modified:
  head/sys/arm64/arm64/locore.S
  head/sys/arm64/include/armreg.h

Modified: head/sys/arm64/arm64/locore.S
==============================================================================
--- head/sys/arm64/arm64/locore.S	Thu Jul 16 10:12:10 2015	(r285625)
+++ head/sys/arm64/arm64/locore.S	Thu Jul 16 10:22:57 2015	(r285626)
@@ -535,7 +535,8 @@ mair:
 		/* Device            Normal, no cache     Normal, write-back */
 	.quad	MAIR_ATTR(0x00, 0) | MAIR_ATTR(0x44, 1) | MAIR_ATTR(0xff, 2)
 tcr:
-	.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K)
+	.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K | \
+	    TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
 sctlr_set:
 	/* Bits to set */
 	.quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \

Modified: head/sys/arm64/include/armreg.h
==============================================================================
--- head/sys/arm64/include/armreg.h	Thu Jul 16 10:12:10 2015	(r285625)
+++ head/sys/arm64/include/armreg.h	Thu Jul 16 10:22:57 2015	(r285626)
@@ -200,6 +200,28 @@
 #define	TCR_TG1_4K	(2 << TCR_TG1_SHIFT)
 #define	TCR_TG1_64K	(3 << TCR_TG1_SHIFT)
 
+#define	TCR_SH1_SHIFT	28
+#define	TCR_SH1_IS	(0x3UL << TCR_SH1_SHIFT)
+#define	TCR_ORGN1_SHIFT	26
+#define	TCR_ORGN1_WBWA	(0x1UL << TCR_ORGN1_SHIFT)
+#define	TCR_IRGN1_SHIFT	24
+#define	TCR_IRGN1_WBWA	(0x1UL << TCR_IRGN1_SHIFT)
+#define	TCR_SH0_SHIFT	12
+#define	TCR_SH0_IS	(0x3UL << TCR_SH0_SHIFT)
+#define	TCR_ORGN0_SHIFT	10
+#define	TCR_ORGN0_WBWA	(0x1UL << TCR_ORGN0_SHIFT)
+#define	TCR_IRGN0_SHIFT	8
+#define	TCR_IRGN0_WBWA	(0x1UL << TCR_IRGN0_SHIFT)
+
+#define	TCR_CACHE_ATTRS	((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
+				(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
+
+#ifdef SMP
+#define	TCR_SMP_ATTRS	(TCR_SH0_IS | TCR_SH1_IS)
+#else
+#define	TCR_SMP_ATTRS	0
+#endif
+
 #define	TCR_T1SZ_SHIFT	16
 #define	TCR_T0SZ_SHIFT	0
 #define	TCR_TxSZ(x)	(((x) << TCR_T1SZ_SHIFT) | ((x) << TCR_T0SZ_SHIFT))