svn commit: r255277 - head/sys/dev/ntb/ntb_hw

[Carl Delsey]

Author: carl
Date: Thu Sep  5 23:06:25 2013
New Revision: 255277
URL: http://svnweb.freebsd.org/changeset/base/255277

Log:
  Cleaning up spacing and making hex value case consistent.
  
  Approved by:	jimharris
  Sponsored by:	Intel

Modified:
  head/sys/dev/ntb/ntb_hw/ntb_regs.h

Modified: head/sys/dev/ntb/ntb_hw/ntb_regs.h
==============================================================================
--- head/sys/dev/ntb/ntb_hw/ntb_regs.h	Thu Sep  5 23:04:36 2013	(r255276)
+++ head/sys/dev/ntb/ntb_hw/ntb_regs.h	Thu Sep  5 23:06:25 2013	(r255277)
@@ -39,14 +39,14 @@
 #define XEON_MAX_SPADS		16
 #define XEON_MAX_COMPAT_SPADS	8
 /* Reserve the uppermost bit for link interrupt */
-#define XEON_MAX_DB_BITS		15
+#define XEON_MAX_DB_BITS	15
 #define XEON_DB_BITS_PER_VEC	5
 
 #define XEON_DB_HW_LINK		0x8000
 
 #define XEON_PCICMD_OFFSET	0x0504
 #define XEON_DEVCTRL_OFFSET	0x0598
-#define XEON_LINK_STATUS_OFFSET	0x01A2
+#define XEON_LINK_STATUS_OFFSET	0x01a2
 
 #define XEON_PBAR2LMT_OFFSET	0x0000
 #define XEON_PBAR4LMT_OFFSET	0x0008
@@ -60,13 +60,13 @@
 #define XEON_SBAR2BASE_OFFSET	0x0048
 #define XEON_SBAR4BASE_OFFSET	0x0050
 #define XEON_NTBCNTL_OFFSET	0x0058
-#define XEON_SBDF_OFFSET		0x005C
+#define XEON_SBDF_OFFSET	0x005c
 #define XEON_PDOORBELL_OFFSET	0x0060
 #define XEON_PDBMSK_OFFSET	0x0062
 #define XEON_SDOORBELL_OFFSET	0x0064
 #define XEON_SDBMSK_OFFSET	0x0066
 #define XEON_USMEMMISS		0x0070
-#define XEON_SPAD_OFFSET		0x0080
+#define XEON_SPAD_OFFSET	0x0080
 #define XEON_SPADSEMA4_OFFSET	0x00c0
 #define XEON_WCCNTRL_OFFSET	0x00e0
 #define XEON_B2B_SPAD_OFFSET	0x0100
@@ -105,7 +105,7 @@
 #define SOC_MODPHY_PCSREG4	0x1c004
 #define SOC_MODPHY_PCSREG6	0x1c006
 
-#define SOC_IP_BASE		0xC000
+#define SOC_IP_BASE		0xc000
 #define SOC_DESKEWSTS_OFFSET	(SOC_IP_BASE + 0x3024)
 #define	SOC_LTSSMERRSTS0_OFFSET (SOC_IP_BASE + 0x3180)
 #define SOC_LTSSMSTATEJMP_OFFSET	(SOC_IP_BASE + 0x3040)
@@ -114,7 +114,7 @@
 #define SOC_DESKEWSTS_DBERR	(1 << 15)
 #define SOC_LTSSMERRSTS0_UNEXPECTEDEI	(1 << 20)
 #define SOC_LTSSMSTATEJMP_FORCEDETECT	(1 << 2)
-#define SOC_IBIST_ERR_OFLOW	0x7FFF7FFF
+#define SOC_IBIST_ERR_OFLOW	0x7fff7fff
 
 #define NTB_CNTL_BAR23_SNOOP	(1 << 2)
 #define NTB_CNTL_BAR45_SNOOP	(1 << 6)
@@ -122,7 +122,7 @@
 
 #define XEON_PBAR23SZ_OFFSET	0x00d0
 #define XEON_PBAR45SZ_OFFSET	0x00d1
-#define NTB_PPD_OFFSET		0x00D4
+#define NTB_PPD_OFFSET		0x00d4
 #define XEON_PPD_CONN_TYPE	0x0003
 #define XEON_PPD_DEV_TYPE	0x0010
 #define SOC_PPD_INIT_LINK	0x0008
@@ -138,11 +138,11 @@
 
 #define SOC_PBAR2XLAT_USD_ADDR	0x0000004000000000
 #define SOC_PBAR4XLAT_USD_ADDR	0x0000008000000000
-#define SOC_MBAR23_USD_ADDR	0x000000410000000C
-#define SOC_MBAR45_USD_ADDR	0x000000810000000C
+#define SOC_MBAR23_USD_ADDR	0x000000410000000c
+#define SOC_MBAR45_USD_ADDR	0x000000810000000c
 #define SOC_PBAR2XLAT_DSD_ADDR	0x0000004100000000
 #define SOC_PBAR4XLAT_DSD_ADDR	0x0000008100000000
-#define SOC_MBAR23_DSD_ADDR	0x000000400000000C
-#define SOC_MBAR45_DSD_ADDR	0x000000800000000C
+#define SOC_MBAR23_DSD_ADDR	0x000000400000000c
+#define SOC_MBAR45_DSD_ADDR	0x000000800000000c
 
 #endif /* _NTB_REGS_H_ */