svn commit: r251715 - head/sys/dev/puc

[Marius Strobl]

Author: marius
Date: Thu Jun 13 22:13:41 2013
New Revision: 251715
URL: http://svnweb.freebsd.org/changeset/base/251715

Log:
  All of Oxford/PLX OX16PCI954, OXm16PCI954 and OXu16PCI954 share the
  exact same (subsystem) device and vendor IDs. However, the reference
  design for the OXu16PCI954 uses a 14.7456 MHz clock (as does the EXSYS
  EX-41098-2 equipped with these), while at least the OX16PCI954 defaults
  to a 1.8432 MHz one. According to the datasheets of these chips, the
  only difference in PCI configuration space is that OXu16PCI954 have
  a revision ID of 1 while the other two are at 0. So employ the latter
  for determining the default clock rates of this family.
  Note that one might think that the actual clock could be derived from
  the Clock Prescaler Register (CPR) of these chips. Unfortunately, this
  is not that case and its use and content are orthogonal to the frequency
  of the crystal employed.
  Tested with an EXSYS EX-41098-2, which identifies and attaches as:
  pcib4 at pci0:19:0:0:      class=0x060400 card=0x02dd1014 chip=0x10801b21
  rev=0x03 hdr=0x01
      vendor     = 'ASMedia Technology Inc.'
      device     = 'ASM1083/1085 PCIe to PCI Bridge'
      class      = bridge
      subclass   = PCI-PCI
  puc0 at pci0:20:4:0:       class=0x070006 card=0x00001415 chip=0x95011415
  rev=0x01 hdr=0x00
      vendor     = 'Oxford Semiconductor Ltd'
      device     = 'OX16PCI954 (Quad 16950 UART) function 0 (Uart)'
      class      = simple comms
      subclass   = UART
  puc1 at pci0:20:4:1:       class=0x068000 card=0x00001415 chip=0x95111415
  rev=0x01 hdr=0x00
      vendor     = 'Oxford Semiconductor Ltd'
      device     = 'OX16PCI954 (Quad 16950 UART) function 1 (8bit bus)'
      class      = bridge
  puc2 at pci0:20:8:0:       class=0x070006 card=0x00001415 chip=0x95011415
  rev=0x01 hdr=0x00
      vendor     = 'Oxford Semiconductor Ltd'
      device     = 'OX16PCI954 (Quad 16950 UART) function 0 (Uart)'
      class      = simple comms
      subclass   = UART
  puc3 at pci0:20:8:1:       class=0x068000 card=0x00001415 chip=0x95111415
  rev=0x01 hdr=0x00
      vendor     = 'Oxford Semiconductor Ltd'
      device     = 'OX16PCI954 (Quad 16950 UART) function 1 (8bit bus)'
      class      = bridge
  
  pci20: <ACPI PCI bus> on pcib4
  puc0: <Oxford Semiconductor OX16PCI954 UARTs> port 0x5000-0x501f,
  0x5020-0x503f mem 0xc6000000-0xc6000fff,0xc6001000-0xc6001fff irq 16 at
  device 4.0 on pci20
  uart1: <16950 or compatible> at port 1 on puc0
  uart2: <16950 or compatible> at port 2 on puc0
  uart3: <16950 or compatible> at port 3 on puc0
  uart4: <16950 or compatible> at port 4 on puc0
  puc1: <Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)> port
  0x5040-0x505f,0x5060-0x507f mem 0xc6002000-0xc6002fff,0xc6003000-0xc6003fff
  irq 16 at device 4.1 on pci20
  puc2: <Oxford Semiconductor OX16PCI954 UARTs> port 0x5080-0x509f,
  0x50a0-0x50bf mem 0xc6004000-0xc6004fff,0xc6005000-0xc6005fff irq 16 at
  device 8.0 on pci20
  uart5: <16950 or compatible> at port 1 on puc2
  uart6: <16950 or compatible> at port 2 on puc2
  uart7: <16950 or compatible> at port 3 on puc2
  uart8: <16950 or compatible> at port 4 on puc2
  puc3: <Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)> port
  0x50c0-0x50df,0x50e0-0x50ff mem 0xc6006000-0xc6006fff,0xc6007000-0xc6007fff
  irq 16 at device 8.1 on pci20
  
  MFC after:	2 weeks

Modified:
  head/sys/dev/puc/pucdata.c

Modified: head/sys/dev/puc/pucdata.c
==============================================================================
--- head/sys/dev/puc/pucdata.c	Thu Jun 13 22:04:49 2013	(r251714)
+++ head/sys/dev/puc/pucdata.c	Thu Jun 13 22:13:41 2013	(r251715)
@@ -53,6 +53,7 @@ static puc_config_f puc_config_exar;
 static puc_config_f puc_config_exar_pcie;
 static puc_config_f puc_config_icbook;
 static puc_config_f puc_config_moxa;
+static puc_config_f puc_config_oxford_pci954;
 static puc_config_f puc_config_oxford_pcie;
 static puc_config_f puc_config_quatech;
 static puc_config_f puc_config_syba;
@@ -743,8 +744,9 @@ const struct puc_cfg puc_pci_devices[] =
 
 	{   0x1415, 0x9501, 0xffff, 0,
 	    "Oxford Semiconductor OX16PCI954 UARTs",
-	    DEFAULT_RCLK,
+	    0,
 	    PUC_PORT_4S, 0x10, 0, 8,
+	    .config_function = puc_config_oxford_pci954
 	},
 
 	{   0x1415, 0x950a, 0x131f, 0x2030,
@@ -1516,6 +1518,28 @@ puc_config_timedia(struct puc_softc *sc,
 }
 
 static int
+puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd,
+    int port __unused, intptr_t *res)
+{
+
+	switch (cmd) {
+	case PUC_CFG_GET_CLOCK:
+		/*
+		 * OXu16PCI954 use a 14.7456 MHz clock by default while
+		 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one.
+		 */
+		if (pci_get_revid(sc->sc_dev) == 1)
+			*res = DEFAULT_RCLK * 8;
+		else
+			*res = DEFAULT_RCLK;
+		return (0);
+	default:
+		break;
+	}
+	return (ENXIO);
+}
+
+static int
 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
     intptr_t *res)
 {