svn commit: r223426 - in head/sys: dev/acpica kern sys x86/x86

[Marcel Moolenaar]

On Jun 22, 2011, at 6:36 PM, Alexander Motin wrote:

> Marcel Moolenaar wrote:
>> On Jun 22, 2011, at 5:30 PM, Alexander Motin wrote:
>>> Marcel Moolenaar wrote:
>>>> On Jun 22, 2011, at 4:24 PM, Jung-uk Kim wrote:
>>>>> I just realized kern_clocksource.c was excluded for arm and ia64.  
>>>>> Here is updated patch.  Please ignore the previous one.
>>>> Any reason why we're not adding kern_clocksource.c for them?
>>> Their event timers code still waits for refactoring. I have neither
>>> documentation nor hardware for them. Help would be appreciated.
>> 
>> Can you give me a pointer to a document orpage that describes
>> what is being refactored, why and how?
> 
> In short, timer management code was unified and formalized. Instead of
> direct programming periodic timers from MD code and calling hard-/
> stat-/ profclock() from there, timer hardware should be exposed to the
> MI kernel using sys/timeet.h API to allow kern_clocksource.c manage it.
> Last require calling its cpu_initclocks_bsp() and cpu_initclocks_ap()
> callbacks from MD initialization code, and cpu_idleclock() and
> cpu_activeclock() from MD cpu_idle().
> 
> Here is some references:
> man 4 eventtimers
> http://wiki.freebsd.org/201010DevSummit?action=AttachFile&do=view&target=timers.pdf
> http://svnweb.freebsd.org/base?view=revision&revision=209371
> http://svnweb.freebsd.org/base?view=revision&revision=212541
> 
> All architectures except ia64 and non-Marvell arm are already done, so
> you may took any of them as reference. Ask me if you have any questions.

Can you give a quick outline of how all the various clock
related initializations and support code relate, interact
or even conflict? It's getting rather convoluted and want
to make sure I get the ordering and timing right.

Also: The ITC on ia64 is a per-CPU, one short and periodic
timer that has a fixed frequency. Though the architecture
does not guarantee that counters are synchronized, nor
that all CPUs in a system run at the same frequency which
means that the ITCs may not all run at the same frequency.
Does the et code work with that or do I need to impose a
restriction on what hardware configurations to support
and/or revert to having the ITC be a global timer and run
only on the BSP?

Thanks,

-- 
Marcel Moolenaar
marcel at xcllnt.net