svn commit: r223426 - in head/sys: dev/acpica kern sys x86/x86

[Jung-uk Kim]

On Wednesday 22 June 2011 12:47 pm, Andriy Gapon wrote:
> on 22/06/2011 19:40 Jung-uk Kim said the following:
> > Author: jkim
> > Date: Wed Jun 22 16:40:45 2011
> > New Revision: 223426
> > URL: http://svn.freebsd.org/changeset/base/223426
> >
> > Log:
> >   Set negative quality to TSC timecounter when C3 state is
> > enabled for Intel processors unless the invariant TSC bit of
> > CPUID is set.  Intel processors may stop incrementing TSC when
> > DPSLP# pin is asserted, according to Intel processor manuals, i.
> > e., TSC timecounter is useless if the processor can enter deep
> > sleep state (C3/C4).  This problem was accidentally uncovered by
> > r222869, which increased timecounter quality of P-state invariant
> > TSC, e.g., for Core2 Duo T5870 (Family 6, Model f) and Atom N270
> > (Family 6, Model 1c).
> >
> >   Reported by:	Fabian Keil (freebsd-listen at fabiankeil dot de)
> >   		Ian FREISLICH (ianf at clue dot co dot za)
> >   Tested by:	Fabian Keil (freebsd-listen at fabiankeil dot de)
> >   		- Core2 Duo T5870 (C3 state available/enabled)
> >   		jkim - Xeon X5150 (C3 state unavailable)
>
> I think that this change should have a counterpart similar to what
> was done for event timers.  That is, if a user forces use of TSC as
> a timecounter vis sysctl and it is known that TSC stops in the deep
> C-state, then the deep C-states should not be entered.  This is
> what cpu_disable_deep_sleep does for LAPIC timers.

Yes.  We have to teach tc_windup() to increase/decrease 
cpu_disable_deep_sleep.  Currently, the user must disable C3 and 
force TSC timecounter manually if power consumption is not important, 
e.g.,

/etc/rc.conf:
economy_cx_lowest="C2"

/etc/sysctl.conf:
kern.timecounter.hardware=TSC

Jung-uk Kim