socsvn commit: r290377 - soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm

[mihai at FreeBSD.org]

Author: mihai
Date: Mon Aug 31 08:08:42 2015
New Revision: 290377
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=290377

Log:
  sys: boot: fdt: dts: arm: fvp_ve-cortex_a15x1.dts: improve interrupts with info about SPI/PPI and trigger type

Modified:
  soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/fvp_ve-cortex_a15x1.dts

Modified: soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/fvp_ve-cortex_a15x1.dts
==============================================================================
--- soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/fvp_ve-cortex_a15x1.dts	Mon Aug 31 08:05:38 2015	(r290376)
+++ soc2015/mihai/bhyve-on-arm-head/sys/boot/fdt/dts/arm/fvp_ve-cortex_a15x1.dts	Mon Aug 31 08:08:42 2015	(r290377)
@@ -43,16 +43,20 @@
 	gic: interrupt-controller at 2c001000 {
 		compatible = "arm,cortex-a15-gic";
 		interrupt-controller;
-		#interrupt-cells = <1>;
+		#interrupt-cells = <3>;
 		reg = <0x2c001000 0x1000>,
 		      <0x2c002000 0x2000>,
 		      <0x2c004000 0x2000>,
 		      <0x2c006000 0x2000>;
+		interrupts = <1 9 0x8>;
 	};
 	generic_timer {
 		compatible = "arm,armv7-timer";
 		clock-frequency = <24000000>;
-		interrupts = < 29 30 27 26 >;
+		interrupts = <1 13 0x4>,
+			     <1 14 0x4>,
+			     <1 11 0x4>,
+			     <1 10 0x4>;
 		interrupt-parent = <&gic>;
 		};
 
@@ -60,41 +64,41 @@
 		compatible = "arm,pl011", "arm,primecell";
 		reg = <0x1c090000 0x1000>;
 		interrupt-parent=<&gic>;
-		interrupts = <37>;
+		interrupts = <0 5 0x4>;
 	};
 
 	v2m_serial1: uart at 1c0a0000 {
 		compatible = "arm,pl011", "arm,primecell";
 		reg = <0x1c0a0000 0x1000>;
 		interrupt-parent=<&gic>;
-		interrupts = <38>;
+		interrupts = <0 6 0x4>;
 	};
 
 	v2m_serial2: uart at 1c0b0000 {
 		compatible = "arm,pl011", "arm,primecell";
 		reg = <0x1c0b0000 0x1000>;
 		interrupt-parent=<&gic>;
-		interrupts = <39>;
+		interrupts = <0 7 0x4>;
 	};
 
 	v2m_serial3: uart at 1c0c0000 {
 		compatible = "arm,pl011", "arm,primecell";
 		reg = <0x1c0c0000 0x1000>;
 		interrupt-parent=<&gic>;
-		interrupts = <40>;
+		interrupts = <0 8 0x4>;
 	};
 	v2m_timer01: timer at 1c110000 {
 		compatible = "arm,sp804", "arm,primecell";
 		reg = <0x1c110000 0x1000>;
 		interrupt-parent=<&gic>;
-		interrupts = <34>;
+		interrupts = <0 2 0x4>;
 	};
 
 	v2m_timer23: timer at 1c120000 {
 		compatible = "arm,sp804", "arm,primecell";
 		reg = <0x1c120000 0x1000>;
 		interrupt-parent=<&gic>;
-		interrupts = <35>;
+		interrupts = <0 3 0x4>;
 	};
 };