socsvn commit: r289596 - in soc2015/mihai/bhyve-on-arm-head/sys/arm: include vmm

[mihai at FreeBSD.org]

Author: mihai
Date: Tue Aug 11 16:37:10 2015
New Revision: 289596
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=289596

Log:
  sys: arm: vmm: hyp.S: save/restore vgic state at each context switch

Modified:
  soc2015/mihai/bhyve-on-arm-head/sys/arm/include/gic.h
  soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.S
  soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp_helpers.h

Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/include/gic.h
==============================================================================
--- soc2015/mihai/bhyve-on-arm-head/sys/arm/include/gic.h	Tue Aug 11 15:53:11 2015	(r289595)
+++ soc2015/mihai/bhyve-on-arm-head/sys/arm/include/gic.h	Tue Aug 11 16:37:10 2015	(r289596)
@@ -1,7 +1,6 @@
 #ifndef _MACHINE_GIC_H_
 #define	_MACHINE_GIC_H_
 
-#include <machine/bus.h>
 
 /* We are using GICv2 register naming */
 
@@ -70,6 +69,8 @@
 #define	GIC_RES_COUNT	3
 #endif
 
+#ifndef __ASSEMBLER__
+#include <machine/bus.h>
 struct arm_gic_softc {
 	device_t		gic_dev;
 	struct resource *	gic_res[GIC_RES_COUNT];
@@ -103,5 +104,6 @@
 #endif
 
 struct arm_gic_softc *get_arm_gic_sc(void);
+#endif
 
 #endif

Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.S
==============================================================================
--- soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.S	Tue Aug 11 15:53:11 2015	(r289595)
+++ soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.S	Tue Aug 11 16:37:10 2015	(r289596)
@@ -30,6 +30,8 @@
 	mcr	p15, 4, r0, c13, c0, 2		@ Store hyp_vmxctx into HTPIDR
 	save_host_regs
 
+	restore_vgic_regs
+
 	/* Save HOST CP15 registers */
 	load_cp15_regs_batch1				@ Load in r2-r12 CP15 regs
 	push {r2-r12}
@@ -128,6 +130,8 @@
 	pop {r2-r12}
 	store_cp15_regs_batch1			@ Load in r2-r12 CP15 regs
 
+	save_vgic_regs
+
 	restore_host_regs
 
 	mov	r0, r1				@ r0 must hold the return value

Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp_helpers.h
==============================================================================
--- soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp_helpers.h	Tue Aug 11 15:53:11 2015	(r289595)
+++ soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp_helpers.h	Tue Aug 11 16:37:10 2015	(r289596)
@@ -1,6 +1,7 @@
 #ifndef _VMM_HYP_HELPERS_H_
 #define	_VMM_HYP_HELPERS_H_
 
+#include <machine/gic.h>
 
 /* Banked registers */
 #define SAVE_GUEST_BANKED_REG(reg)		\
@@ -256,4 +257,64 @@
 	ldr	r3, [r0, #HYPCTX_CP15_AMAIR0];			\
 	ldr	r6, [r0, #HYPCTX_CP15_AMAIR1]
 
+
+#define save_vgic_regs						\
+	ldr	r2, [r0, #HYPCTX_VGIC_INT_CTRL];		\
+	cmp	r2, #0;						\
+	beq	1f;						\
+								\
+	ldr	r3, [r2, #GICH_HCR];				\
+	str	r3, [r0, #HYPCTX_VGIC_HCR];			\
+								\
+	ldr	r3, [r2, #GICH_VMCR];				\
+	str	r3, [r0, #HYPCTX_VGIC_VMCR];			\
+								\
+	ldr	r3, [r2, #GICH_MISR];				\
+	str	r3, [r0, #HYPCTX_VGIC_MISR];			\
+								\
+	ldr	r3, [r2, #GICH_EISR0];				\
+	ldr	r4, [r2, #GICH_EISR1];				\
+	str	r3, [r2, #HYPCTX_VGIC_EISR];			\
+	str	r4, [r2, #(HYPCTX_VGIC_EISR + 4)];		\
+								\
+	ldr	r3, [r2, #GICH_ELSR0];				\
+	ldr	r4, [r2, #GICH_ELSR1];				\
+	str	r3, [r0, #HYPCTX_VGIC_ELSR];			\
+	str	r4, [r0, #(HYPCTX_VGIC_ELSR + 4)];		\
+								\
+	ldr	r3, [r2, #GICH_APR];				\
+	str 	r3, [r0, #HYPCTX_VGIC_APR];			\
+								\
+	ldr	r3, [r0, #HYPCTX_VGIC_LR_NUM];			\
+	add	r4, r2, #GICH_LR0;				\
+	add	r5, r0, #HYPCTX_VGIC_LR;			\
+2:	ldr	r6, [r4], #4;					\
+	str	r6, [r5], #4;					\
+	subs	r3, r3, #1;					\
+	bne	2b;						\
+1:
+
+#define restore_vgic_regs					\
+	ldr	r2, [r0, #HYPCTX_VGIC_INT_CTRL];		\
+	cmp	r2, #0;						\
+	beq	3f;						\
+								\
+	ldr	r3, [r0, #HYPCTX_VGIC_HCR];			\
+	str	r3, [r2, #GICH_HCR];				\
+								\
+	ldr	r3, [r0, #HYPCTX_VGIC_VMCR];			\
+	str	r3, [r2, #GICH_VMCR];				\
+								\
+	str 	r3, [r0, #HYPCTX_VGIC_APR];			\
+	ldr	r3, [r2, #GICH_APR];				\
+								\
+	ldr	r3, [r0, #HYPCTX_VGIC_LR_NUM];			\
+	add	r4, r2, #GICH_LR0;				\
+	add	r5, r0, #HYPCTX_VGIC_LR;			\
+4:	ldr	r6, [r5], #4;					\
+	str	r6, [r4], #4;					\
+	subs	r3, r3, #1;					\
+	bne	4b;						\
+3:
+
 #endif