socsvn commit: r237465 - in soc2012/aleek/beaglexm-armv6/sys:
arm/arm arm/conf arm/ti arm/ti/am37x boot/fdt/dts
aleek at FreeBSD.org
aleek at FreeBSD.org
Mon Jun 11 13:22:48 UTC 2012
Author: aleek
Date: Mon Jun 11 13:22:45 2012
New Revision: 237465
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=237465
Log:
minor changes to initarm() to make kernel boots the entire initarm()
Modified:
soc2012/aleek/beaglexm-armv6/sys/arm/arm/cpufunc_asm_armv7.S
soc2012/aleek/beaglexm-armv6/sys/arm/arm/locore.S
soc2012/aleek/beaglexm-armv6/sys/arm/conf/BEAGLEBOARD-XM
soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_early_uart.c
soc2012/aleek/beaglexm-armv6/sys/arm/ti/ti_cpuid.c
soc2012/aleek/beaglexm-armv6/sys/arm/ti/ti_machdep.c
soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts
Modified: soc2012/aleek/beaglexm-armv6/sys/arm/arm/cpufunc_asm_armv7.S
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/arm/arm/cpufunc_asm_armv7.S Mon Jun 11 12:34:14 2012 (r237464)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/arm/cpufunc_asm_armv7.S Mon Jun 11 13:22:45 2012 (r237465)
@@ -1,5 +1,8 @@
/*-
- * Copyright (c) 2010 Per Odlund <per.odlund at armagedon.se>
+ * Copyright (C) 2011 MARVELL INTERNATIONAL LTD.
+ * All rights reserved.
+ *
+ * Developed by Semihalf.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -9,54 +12,67 @@
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of MARVELL nor the names of contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/* ARMv7 assembly functions for manipulating caches and other core functions.
- * Based on cpufuncs for v6 and xscale.
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
*/
-
#include <machine/asm.h>
+__FBSDID("$FreeBSD$");
-#define entrysize #32
-
-ENTRY(armv7_cpu_sleep)
- tst r0, #0x00000000 /* shouldn't sleep 0 */
- RET
-
-
-ENTRY(armv7_wait)
- mrc p15, 0, r0, c2, c0, 0 /* arbitrary read of CP15 */
- add r0, r0, #0 /* a stall */
+.Lcoherency_level:
+ .word _C_LABEL(arm_cache_loc)
+.Lcache_type:
+ .word _C_LABEL(arm_cache_type)
+.Lway_mask:
+ .word 0x3ff
+.Lmax_index:
+ .word 0x7fff
+.Lpage_mask:
+ .word 0xfff
+
+#define PT_NOS (1 << 5)
+#define PT_S (1 << 1)
+#define PT_INNER_NC 0
+#define PT_INNER_WT (1 << 0)
+#define PT_INNER_WB ((1 << 0) | (1 << 6))
+#define PT_INNER_WBWA (1 << 6)
+#define PT_OUTER_NC 0
+#define PT_OUTER_WT (2 << 3)
+#define PT_OUTER_WB (3 << 3)
+#define PT_OUTER_WBWA (1 << 3)
+
+#ifdef SMP
+#define PT_ATTR (PT_S|PT_INNER_WT|PT_OUTER_WT|PT_NOS)
+#else
+#define PT_ATTR (PT_INNER_WT|PT_OUTER_WT)
+#endif
+
+ENTRY(armv7_setttb2)
+ stmdb sp!, {r0, lr}
+ bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */
+ ldmia sp!, {r0, lr}
+ dsb
+
+ orr r0, r0, #PT_ATTR
+ mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */
+ mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
+ dsb
+ isb
RET
-
-ENTRY(armv7_context_switch)
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
- mcr p15, 0, r0, c8, c7, 0 /* flush the I+D */
- RET
-
-
-ENTRY(armv7_tlb_flushID_SE)
- mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
- mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
- RET
-
-
-
ENTRY(armv7_setttb)
stmdb sp!, {r0, lr}
bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */
@@ -68,91 +84,203 @@
RET
-/* Cache operations. */
-
-/* LINTSTUB: void armv7_icache_sync_range(vaddr_t, vsize_t); */
-ENTRY_NP(armv7_icache_sync_range)
-1:
- mcr p15, 0, r0, c7, c5, 1 /* invalidate the I-Cache line */
- mcr p15, 0, r0, c7, c10, 1 /* wb the D-Cache line */
- add r0, r0, entrysize
- subs r1, r1, entrysize
- bhi 1b
-
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */
- RET
-
+ENTRY(armv7_tlb_flushID)
+ dsb
+#ifdef SMP
+ mcr p15, 0, r0, c8, c3, 0
+#else
+ mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
+#endif
+ mcr p15, 0, r0, c7, c5, 6 /* flush BTB */
+ dsb
+ isb
+ mov pc, lr
-/* LINTSTUB: void armv7_icache_sync_all(void); */
-ENTRY_NP(armv7_icache_sync_all)
- /*
- * We assume that the code here can never be out of sync with the
- * dcache, so that we can safely flush the Icache and fall through
- * into the Dcache cleaning code.
- */
- stmdb sp!, {r0, lr}
- bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */
- ldmia sp!, {r0, lr}
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */
+ENTRY(armv7_tlb_flushID_SE)
+ ldr r1, .Lpage_mask
+ bic r0, r0, r1
+#ifdef SMP
+ mcr p15, 0, r0, c8, c3, 1 /* flush D tlb single entry */
+#else
+ mcr p15, 0, r0, c8, c7, 1 /* flush D tlb single entry */
+#endif
+ mcr p15, 0, r0, c7, c5, 6 /* flush BTB */
+ dsb
+ isb
+ mov pc, lr
+
+/* Based on algorithm from ARM Architecture Reference Manual */
+ENTRY(armv7_dcache_wbinv_all)
+ stmdb sp!, {r4, r5, r6, r7, r8, r9}
+
+ /* Get cache level */
+ ldr r0, .Lcoherency_level
+ ldr r3, [r0]
+ cmp r3, #0
+ beq Finished
+ /* For each cache level */
+ mov r8, #0
+Loop1:
+ /* Get cache type for given level */
+ mov r2, r8, lsl #2
+ add r2, r2, r2
+ ldr r0, .Lcache_type
+ ldr r1, [r0, r2]
+
+ /* Get line size */
+ and r2, r1, #7
+ add r2, r2, #4
+
+ /* Get number of ways */
+ ldr r4, .Lway_mask
+ ands r4, r4, r1, lsr #3
+ clz r5, r4
+
+ /* Get max index */
+ ldr r7, .Lmax_index
+ ands r7, r7, r1, lsr #13
+Loop2:
+ mov r9, r4
+Loop3:
+ mov r6, r8, lsl #1
+ orr r6, r6, r9, lsl r5
+ orr r6, r6, r7, lsl r2
+
+ /* Clean and invalidate data cache by way/index */
+ mcr p15, 0, r6, c7, c14, 2
+ subs r9, r9, #1
+ bge Loop3
+ subs r7, r7, #1
+ bge Loop2
+Skip:
+ add r8, r8, #1
+ cmp r3, r8
+ bne Loop1
+Finished:
+ dsb
+ ldmia sp!, {r4, r5, r6, r7, r8, r9}
+ RET
+
+ENTRY(armv7_idcache_wbinv_all)
+ stmdb sp!, {lr}
+ bl armv7_dcache_wbinv_all
+ mcr p15, 0, r0, c7, c5, 0 /* Invalidate all I caches to PoU (ICIALLU) */
+ dsb
+ isb
+ ldmia sp!, {lr}
RET
+/* XXX Temporary set it to 32 for MV cores, however this value should be
+ * get from Cache Type register
+ */
+.Larmv7_line_size:
+ .word 32
-/* LINTSTUB: armv7_dcache_wb_range(vaddr_t, vsize_t); */
ENTRY(armv7_dcache_wb_range)
-1:
- mcr p15, 0, r0, c7, c10, 1 /* wb the D-Cache */
- add r0, r0, entrysize
- subs r1, r1, entrysize
- bhi 1b
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */
+ ldr ip, .Larmv7_line_size
+ sub r3, ip, #1
+ and r2, r0, r3
+ add r1, r1, r2
+ bic r0, r0, r3
+.Larmv7_wb_next:
+ mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
+ add r0, r0, ip
+ subs r1, r1, ip
+ bhi .Larmv7_wb_next
+ dsb /* data synchronization barrier */
RET
-
-/* LINTSTUB: void armv7_dcache_wbinv_range(vaddr_t, vsize_t); */
ENTRY(armv7_dcache_wbinv_range)
-1:
- mcr p15, 0, r0, c7, c14, 1 /* wb and inv the D-Cache line */
- add r0, r0, entrysize
- subs r1, r1, entrysize
- bhi 1b
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */
+ ldr ip, .Larmv7_line_size
+ sub r3, ip, #1
+ and r2, r0, r3
+ add r1, r1, r2
+ bic r0, r0, r3
+.Larmv7_wbinv_next:
+ mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
+ add r0, r0, ip
+ subs r1, r1, ip
+ bhi .Larmv7_wbinv_next
+ dsb /* data synchronization barrier */
RET
-/* * LINTSTUB: void armv7_dcache_inv_range(vaddr_t, vsize_t); */
+/*
+ * Note, we must not invalidate everything. If the range is too big we
+ * must use wb-inv of the entire cache.
+ */
ENTRY(armv7_dcache_inv_range)
-1:
- mcr p15, 0, r0, c7, c6, 1 /* invalidate the D-Cache line */
- add r0, r0, entrysize
- subs r1, r1, entrysize
- bhi 1b
+ ldr ip, .Larmv7_line_size
+ sub r3, ip, #1
+ and r2, r0, r3
+ add r1, r1, r2
+ bic r0, r0, r3
+.Larmv7_inv_next:
+ mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
+ add r0, r0, ip
+ subs r1, r1, ip
+ bhi .Larmv7_inv_next
+ dsb /* data synchronization barrier */
+ RET
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */
+ENTRY(armv7_idcache_wbinv_range)
+ ldr ip, .Larmv7_line_size
+ sub r3, ip, #1
+ and r2, r0, r3
+ add r1, r1, r2
+ bic r0, r0, r3
+.Larmv7_id_wbinv_next:
+ mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
+ mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
+ add r0, r0, ip
+ subs r1, r1, ip
+ bhi .Larmv7_id_wbinv_next
+ isb /* instruction synchronization barrier */
+ dsb /* data synchronization barrier */
RET
+ENTRY_NP(armv7_icache_sync_range)
+ ldr ip, .Larmv7_line_size
+.Larmv7_sync_next:
+ mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
+ mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
+ add r0, r0, ip
+ subs r1, r1, ip
+ bhi .Larmv7_sync_next
+ isb /* instruction synchronization barrier */
+ dsb /* data synchronization barrier */
+ RET
-ENTRY(armv7_idcache_wbinv_range)
-1:
- mcr p15, 0, r0, c7, c5, 1 /* invalidate the I-Cache line */
- mcr p15, 0, r0, c7, c14, 1 /* wb and inv the D-Cache line */
- add r0, r0, entrysize
- subs r1, r1, entrysize
- bhi 1b
-
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer, BSB */
+ENTRY(armv7_cpu_sleep)
+ dsb /* data synchronization barrier */
+ wfi /* wait for interrupt */
RET
+ENTRY(armv7_context_switch)
+ dsb
+ orr r0, r0, #PT_ATTR
+
+ mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
+ mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
+ dsb
+ isb
+ RET
-ENTRY_NP(armv7_idcache_wbinv_all)
- /*
- * We assume that the code here can never be out of sync with the
- * dcache, so that we can safely flush the Icache and fall through
- * into the Dcache purging code.
- */
- mcr p15, 0, r0, c7, c5, 0
- b _C_LABEL(armv7_dcache_wbinv_all)
+ENTRY(armv7_drain_writebuf)
+ dsb
+ RET
+ENTRY(armv7_sev)
+ dsb
+ sev
+ nop
+ RET
-/*
- * armv7_dcache_wbinv_all is in cpufunc.c. It's really too long to
- * write in assembler.
- */
+ENTRY(armv7_auxctrl)
+ mrc p15, 0, r2, c1, c0, 1
+ bic r3, r2, r0 /* Clear bits */
+ eor r3, r3, r1 /* XOR bits */
+
+ teq r2, r3
+ mcrne p15, 0, r3, c1, c0, 1
+ mov r0, r2
+ RET
Modified: soc2012/aleek/beaglexm-armv6/sys/arm/arm/locore.S
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/arm/arm/locore.S Mon Jun 11 12:34:14 2012 (r237464)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/arm/locore.S Mon Jun 11 13:22:45 2012 (r237465)
@@ -247,7 +247,7 @@
MMU_INIT(0x48000000, 0x48000000, 1, L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW))
#endif
/*MMU_INIT(0x49020000, 0x49020000, 1, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))*/
- MMU_INIT(0x49000000, 0x49000000, 1, L1_TYPE_S|L1_S_AP(AP_KRW))
+ MMU_INIT(0xe9000000, 0x49000000, 1, L1_TYPE_S|L1_S_AP(AP_KRW))
.word 0 /* end of table */
#endif
.Lstart:
Modified: soc2012/aleek/beaglexm-armv6/sys/arm/conf/BEAGLEBOARD-XM
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/arm/conf/BEAGLEBOARD-XM Mon Jun 11 12:34:14 2012 (r237464)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/conf/BEAGLEBOARD-XM Mon Jun 11 13:22:45 2012 (r237465)
@@ -50,7 +50,7 @@
# Debugging
makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
options BREAK_TO_DEBUGGER
-#options VERBOSE_SYSINIT #Enable verbose sysinit messages
+#options VERBOSE_SYSINIT #Enable verbose sysinit messages
options KDB
options DDB #Enable the kernel debugger
options INVARIANTS #Enable calls of extra sanity checking
Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_early_uart.c
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_early_uart.c Mon Jun 11 12:34:14 2012 (r237464)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/am37x/am37x_early_uart.c Mon Jun 11 13:22:45 2012 (r237465)
@@ -50,8 +50,8 @@
void
arm_early_putc( char c )
{
- volatile uint32_t *uart = (volatile uint32_t *)0x49020000;
- volatile uint32_t *uart_lsr = (volatile uint32_t *)0x49020014;
+ volatile uint32_t *uart = (volatile uint32_t *)0xe9020000;
+ volatile uint32_t *uart_lsr = (volatile uint32_t *)0xe9020014;
while ((*uart_lsr & 0x20) == 0);
*uart = c;
Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/ti_cpuid.c
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/arm/ti/ti_cpuid.c Mon Jun 11 12:34:14 2012 (r237464)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/ti_cpuid.c Mon Jun 11 13:22:45 2012 (r237465)
@@ -253,6 +253,12 @@
cpu_last_char, AM335X_DEVREV(chip_revision));
}
+/* static void
+am37x_get_revision(void)
+{
+ // XXX @TODO fix this
+ printf( "Texas Instruments AM37x HABABABA Processor - FIXME bejbe\n" );
+}*/
/**
* ti_cpu_ident - attempts to identify the chip we are running on
* @dummy: ignored
@@ -277,6 +283,10 @@
case CHIP_AM335X:
am335x_get_revision();
break;
+ case CHIP_AM37X:
+ omap3_get_revision();
+ //am37x_get_revision();
+ break;
default:
panic("Unknown chip type, fixme!\n");
}
Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/ti_machdep.c
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/arm/ti/ti_machdep.c Mon Jun 11 12:34:14 2012 (r237464)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/ti_machdep.c Mon Jun 11 13:22:45 2012 (r237465)
@@ -560,7 +560,9 @@
*/
OF_interpret("perform-fixup", 0);
+ arm_early_puts( "cninit()..." );
cninit();
+ arm_early_puts( "done!\n" );
physmem = memsize / PAGE_SIZE;
@@ -629,6 +631,8 @@
/* Do basic tuning, hz etc */
init_param2(physmem);
+
+ debugf("initarm: kdb_init()\n");
kdb_init();
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
Modified: soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts Mon Jun 11 12:34:14 2012 (r237464)
+++ soc2012/aleek/beaglexm-armv6/sys/boot/fdt/dts/beagleboardxm.dts Mon Jun 11 13:22:45 2012 (r237465)
@@ -41,10 +41,10 @@
memory {
device_type = "memory";
- reg = < 0x80000000 0x10000000 >; /* 256MB RAM */
+ reg = < 0x80000000 0x20000000 >; /* 256MB RAM */
};
- SOC: am335x {
+ SOC: am37x {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@@ -59,48 +59,8 @@
reg = < 0x48200000 0x1000 >;
};
- scm at 44e10000 {
- compatible = "ti,scm";
- reg = < 0x44e10000 0x2000 >;
- /* Set of triplets < padname, muxname, padstate> */
- scm-pad-config =
- /* I2C0 */
- "I2C0_SDA", "I2C0_SDA","input_pullup_inact_slow",
- "I2C0_SCL", "I2C0_SCL","input_pullup_inact_slow",
- /* Ethernet */
- "MII1_RX_ER", "gmii1_rxerr", "input",
- "MII1_TX_EN", "gmii1_txen", "output",
- "MII1_RX_DV", "gmii1_rxdv", "input",
- "MII1_TXD3", "gmii1_txd3", "output",
- "MII1_TXD2", "gmii1_txd2", "output",
- "MII1_TXD1", "gmii1_txd1", "output",
- "MII1_TXD0", "gmii1_txd0", "output",
- "MII1_TX_CLK", "gmii1_txclk", "input",
- "MII1_RX_CLK", "gmii1_rxclk", "input",
- "MII1_RXD3", "gmii1_rxd3", "input",
- "MII1_RXD2", "gmii1_rxd2", "input",
- "MII1_RXD1", "gmii1_rxd1", "input",
- "MII1_RXD0", "gmii1_rxd0", "input",
- "MDIO", "mdio_data", "input_pullup_inact",
- "MDC", "mdio_clk", "output_pullup",
- /* MMCSD0 */
- "MMC0_CMD", "mmc0_cmd", "input_pullup_inact",
- "MMC0_CLK", "mmc0_clk", "input_pullup_inact",
- "MMC0_DAT0", "mmc0_dat0", "input_pullup_inact",
- "MMC0_DAT1", "mmc0_dat1", "input_pullup_inact",
- "MMC0_DAT2", "mmc0_dat2", "input_pullup_inact",
- "MMC0_DAT3", "mmc0_dat3", "input_pullup_inact";
- };
-
- prcm at 44E00000 {
- compatible = "am335x,prcm";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = < 0x44E00000 0x1300 >;
- };
-
dmtimers at 44E05000 {
- compatible = "ti,am335x-dmtimer";
+ compatible = "ti,am37x-dmtimer";
#address-cells = <1>;
#size-cells = <1>;
reg = < 0x44E05000 0x1000
@@ -115,74 +75,27 @@
interrupt-parent = <&AINTC>;
};
- GPIO: gpio {
- #gpio-cells = <3>;
- compatible = "ti,gpio";
- gpio-controller;
- reg =< 0x44E07000 0x1000
- 0x4804C000 0x1000
- 0x481AC000 0x1000
- 0x481AE000 0x1000 >;
- interrupts = < 17 19 21 23 >;
- interrupt-parent = <&AINTC>;
- };
-
-
- uart0: serial at 44E09000 {
+ uart0: serial at 49020000 {
compatible = "ns16550";
- reg = <0x44E09000 0x1000>;
+ reg = <0x49020000 0x1000>;
reg-shift = <2>;
- interrupts = < 72 >;
+ interrupts = < 74 >;
interrupt-parent = <&AINTC>;
clock-frequency = < 48000000 >; /* FIXME */
};
- edma3 at 49000000 {
- compatible = "ti,edma3";
- reg =< 0x49000000 0x100000 /* Channel Controller Regs */
- 0x49800000 0x100000 /* Transfer Controller 0 Regs */
- 0x49900000 0x100000 /* Transfer Controller 1 Regs */
- 0x49a00000 0x100000 >; /* Transfer Controller 2 Regs */
- interrupts = <12 13 14>;
- interrupt-parent = <&AINTC>;
- };
-
- mmchs0 at 4809C000 {
- compatible = "ti,mmchs";
- reg =<0x48060000 0x1000 >;
- interrupts = <64>;
- interrupt-parent = <&AINTC>;
- mmchs-device-id = <0>;
- };
- enet0: ethernet at 4A100000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "ti,cpsw";
- reg = <0x4A100000 0x3000>;
- interrupts = <40 41 42 43>;
- interrupt-parent = <&AINTC>;
- phy-handle = <&phy0>;
- mdio at 0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ti,cpsw-mdio";
- phy0: ethernet-phy at 0 {
- reg = <0x0>;
- };
- };
- };
- i2c0: i2c at 44e0b000 {
+ i2c0: i2c at 48070000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,i2c";
- reg =< 0x44e0b000 0x1000 >;
- interrupts = <70>;
+ reg =< 0x48070000 0x1000 >;
+ interrupts = <56>;
interrupt-parent = <&AINTC>;
i2c-device-id = <0>;
pmic at 24 {
- compatible = "ti,am335x-pmic";
+ compatible = "ti,am37x-pmic";
reg = <0x24>;
};
};
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