socsvn commit: r240504 - soc2012/aleek/beaglexm-armv6/sys/arm/ti/twl

[aleek at FreeBSD.org]

Author: aleek
Date: Sat Aug 18 20:26:49 2012
New Revision: 240504
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=240504

Log:
  fixed bug in twl_vreg module. The reg offset was not right - need to change it correctly to the datasheet. Remember to check both linux kernel AND datasheet :)

Modified:
  soc2012/aleek/beaglexm-armv6/sys/arm/ti/twl/twl_vreg.c

Modified: soc2012/aleek/beaglexm-armv6/sys/arm/ti/twl/twl_vreg.c
==============================================================================
--- soc2012/aleek/beaglexm-armv6/sys/arm/ti/twl/twl_vreg.c	Sat Aug 18 19:25:00 2012	(r240503)
+++ soc2012/aleek/beaglexm-armv6/sys/arm/ti/twl/twl_vreg.c	Sat Aug 18 20:26:49 2012	(r240504)
@@ -176,12 +176,12 @@
 	TWL_REGULATOR_ADJUSTABLE("vaux4",    3, 0x7E, twl4030_vaux4_voltages),
 	TWL_REGULATOR_ADJUSTABLE("vmmc1",    3, 0x82, twl4030_vmmc1_voltages),
 	TWL_REGULATOR_ADJUSTABLE("vmmc2",    3, 0x86, twl4030_vmmc2_voltages),
-	TWL_REGULATOR_ADJUSTABLE("vpll1",    0, 0x8A, twl4030_vpll1_voltages),
-	TWL_REGULATOR_ADJUSTABLE("vpll2",    0, 0x8E, twl4030_vpll2_voltages),
-	TWL_REGULATOR_ADJUSTABLE("vsim",     0, 0x92, twl4030_vsim_voltages),
-	TWL_REGULATOR_ADJUSTABLE("vdac",     0, 0x96, twl4030_vdac_voltages),
-	TWL_REGULATOR_ADJUSTABLE("vintana2", 0, 0x9E, twl4030_vintana2_voltages),
-	TWL_REGULATOR_FIXED("vintana1", 3, 0x92, 1500),
+	TWL_REGULATOR_ADJUSTABLE("vpll1",    3, 0x8A, twl4030_vpll1_voltages),
+	TWL_REGULATOR_ADJUSTABLE("vpll2",    3, 0x8E, twl4030_vpll2_voltages),
+	TWL_REGULATOR_ADJUSTABLE("vsim",     3, 0x92, twl4030_vsim_voltages),
+	TWL_REGULATOR_ADJUSTABLE("vdac",     3, 0x96, twl4030_vdac_voltages),
+	TWL_REGULATOR_ADJUSTABLE("vintana2", 3, 0x9E, twl4030_vintana2_voltages),
+	TWL_REGULATOR_FIXED("vintana1", 3, 0x9A, 1500),
 	TWL_REGULATOR_FIXED("vintdig",  3, 0xA2, 1500),
 	TWL_REGULATOR_FIXED("vusb1v5",  3, 0xCC, 1500),
 	TWL_REGULATOR_FIXED("vusb1v8",  3, 0xCF, 1800),
@@ -229,7 +229,7 @@
 	LIST_HEAD(twl_regulator_list, twl_regulator_entry) sc_vreg_list;
 };
 
-#if 1
+
 #define TWL_VREG_XLOCK(_sc)			sx_xlock(&(_sc)->sc_sx)
 #define	TWL_VREG_XUNLOCK(_sc)		sx_xunlock(&(_sc)->sc_sx)
 #define TWL_VREG_SLOCK(_sc)			sx_slock(&(_sc)->sc_sx)
@@ -245,21 +245,6 @@
 			pause("twl_vreg_ex", (hz / 100));    \
 	} while(0)
 #define TWL_VREG_LOCK_DOWNGRADE(_sc)	sx_downgrade(&(_sc)->sc_sx);
-#endif
-
-#if 0
-#define TWL_VREG_XLOCK(_sc)
-#define	TWL_VREG_XUNLOCK(_sc)
-#define TWL_VREG_SLOCK(_sc)
-#define	TWL_VREG_SUNLOCK(_sc)
-#define TWL_VREG_LOCK_INIT(_sc)
-#define TWL_VREG_LOCK_DESTROY(_sc)
-
-#define TWL_VREG_ASSERT_LOCKED(_sc)
-
-#define TWL_VREG_LOCK_UPGRADE(_sc)
-#define TWL_VREG_LOCK_DOWNGRADE(_sc)
-#endif
 
 
 
@@ -697,7 +682,7 @@
 	
 //#ifdef DEBUG
 	if (!err)
-		device_printf(sc->sc_dev, "%s : reading voltage is %dmV (vsel: 0x%x)\n",
+		device_printf(sc->sc_dev, "%s : read voltage is %dmV (vsel: 0x%x)\n",
 		    regulator->name, *millivolts, vsel);
 //#endif