[GSOC] bhyve instruction caching

[Mihai Carabas]

>
> These days I've started a discussion with Neel about some
> microbenchmarking mechanisms. I will come with some more details next
> week.
I've built a microbenchmarking kernel module which is accessing the
lapic->id for 1000000 and than I calculate the average of an access
(each access needs to be emulated by the hypervisor).

I've also implemented the instuction caching mechanism. At each emulation:
- I check to see if I have that particular instruction cached
- if not I will cache it in a particula structure named "struct vie_cached" [1]
- if it's cached I just use that instruction

Right now I am working on write-protecting the pages where the
instruction reside. I will come with some more details/results when I
finished this part too (there are some SMP issues I'm still debating
with Neel).

[1] https://socsvn.freebsd.org/socsvn/soc2014/mihai/bhyve-icache-head/sys/amd64/vmm/vmm_instruction_cache.c
[2] https://socsvn.freebsd.org/socsvn/soc2014/mihai/lapic_test/lapic_test.c

Thanks,
Mihai