PERFORCE change 1124302 for review
Brooks Davis
brooks at FreeBSD.org
Thu Oct 17 19:49:22 UTC 2013
http://p4web.freebsd.org/@@1124302?ac=10
Change 1124302 by brooks at brooks_zenith on 2013/10/17 19:49:21
Reduce diffs between BERI platforms:
- Enable enterupts on SIM JTAG UART
- Add a WAG at approprate peripherals to the tPad config
- Lots of whitespace deltas
Affected files ...
.. //depot/projects/ctsrd/beribsd/src/sys/boot/fdt/dts/beri-sim.dts#6 edit
.. //depot/projects/ctsrd/beribsd/src/sys/boot/fdt/dts/beripad-de4.dts#27 edit
.. //depot/projects/ctsrd/beribsd/src/sys/boot/fdt/dts/beripad-tpad.dts#4 edit
Differences ...
==== //depot/projects/ctsrd/beribsd/src/sys/boot/fdt/dts/beri-sim.dts#6 (text+ko) ====
@@ -1,5 +1,6 @@
/*-
* Copyright (c) 2012-2013 Robert N. M. Watson
+ * Copyright (c) 2013 SRI International
* All rights reserved.
*
* This software was developed by SRI International and the University of
@@ -101,10 +102,10 @@
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
- reg= <0x7f804000 0x400
- 0x7f806000 0x10
- 0x7f806080 0x10
- 0x7f806100 0x10>;
+ reg = <0x7f804000 0x400
+ 0x7f806000 0x10
+ 0x7f806080 0x10
+ 0x7f806100 0x10>;
interrupts = <0 1 2 3 4>;
hard-interrupt-sources = <64>;
soft-interrupt-sources = <64>;
@@ -113,7 +114,8 @@
serial at 7f000000 {
compatible = "altera,jtag_uart-11_0";
reg = <0x7f000000 0x40>;
- //interrupts = <0>;
+ interrupts = <0>;
+ interrupt-parent = <&beripic>;
};
serial at 7f001000 {
==== //depot/projects/ctsrd/beribsd/src/sys/boot/fdt/dts/beripad-de4.dts#27 (text+ko) ====
@@ -53,7 +53,7 @@
/*
* Secondary CPUs all start disabled and use the
- * spin-table enable method. cpu-release-addr must be
+ * spin-table enable method. cpu-release-addr must be
* specified for each cpu other than cpu at 0. Values of
* cpu-release-addr grow down from 0x100000 (kernel).
*/
@@ -63,7 +63,7 @@
cpu at 0 {
device-type = "cpu";
compatible = "sri-cambridge,beri";
-
+
reg = <0>;
status = "okay";
};
@@ -72,11 +72,11 @@
cpu at 1 {
device-type = "cpu";
compatible = "sri-cambridge,beri";
-
+
reg = <1>;
// XXX: should we need cached prefix?
cpu-release-addr = <0xffffffff 0x800fffe0>;
- }
+ };
*/
};
@@ -102,27 +102,23 @@
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
- reg = <0x7f804000 0x400
- 0x7f806000 0x10
- 0x7f806080 0x10
- 0x7f806100 0x10>;
+ reg = <0x7f804000 0x400
+ 0x7f806000 0x10
+ 0x7f806080 0x10
+ 0x7f806100 0x10>;
interrupts = <0 1 2 3 4>;
hard-interrupt-sources = <64>;
soft-interrupt-sources = <64>;
- /*
- * Ideally we'd have phandle to our core here so we
- * can query things like nthreads.
- */
- }
+ };
- serial at 7f002100 {
- compatible = "ns16550";
- reg = <0x7f002100 0x20>;
- reg-shift = <2>;
- clock-frequency = <50000000>;
- interrupts = <6>;
- interrupt-parent = <&beripic>;
- };
+ serial at 7f002100 {
+ compatible = "ns16550";
+ reg = <0x7f002100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <50000000>;
+ interrupts = <6>;
+ interrupt-parent = <&beripic>;
+ };
serial at 7f000000 {
compatible = "altera,jtag_uart-11_0";
@@ -196,10 +192,10 @@
compatible = "altera,atse";
// MAC, RX+RXC, TX+TXC.
reg = <0x7f007000 0x400
- 0x7f007500 0x8
- 0x7f007520 0x20
- 0x7f007400 0x8
- 0x7f007420 0x20>;
+ 0x7f007500 0x8
+ 0x7f007520 0x20
+ 0x7f007400 0x8
+ 0x7f007420 0x20>;
// RX, TX
interrupts = <1 2>;
interrupt-parent = <&beripic>;
@@ -209,10 +205,10 @@
compatible = "altera,atse";
// MAC, RX+RXC, TX+TXC.
reg = <0x7f005000 0x400
- 0x7f005500 0x8
- 0x7f005520 0x20
- 0x7f005400 0x8
- 0x7f005420 0x20>;
+ 0x7f005500 0x8
+ 0x7f005520 0x20
+ 0x7f005400 0x8
+ 0x7f005420 0x20>;
// RX, TX
interrupts = <11 12>;
interrupt-parent = <&beripic>;
==== //depot/projects/ctsrd/beribsd/src/sys/boot/fdt/dts/beripad-tpad.dts#4 (text+ko) ====
@@ -1,5 +1,6 @@
/*-
* Copyright (c) 2012-2013 Robert N. M. Watson
+ * Copyright (c) 2013 SRI International
* All rights reserved.
*
* This software was developed by SRI International and the University of
@@ -41,15 +42,42 @@
*/
/ {
- model = "SRI/Cambridge BeriPad (DE4)";
+ model = "SRI/Cambridge BeriPad (tPad)";
compatible = "sri-cambridge,beripad-de4";
#address-cells = <1>;
#size-cells = <1>;
cpus {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * Secondary CPUs all start disabled and use the
+ * spin-table enable method. cpu-release-addr must be
+ * specified for each cpu other than cpu at 0. Values of
+ * cpu-release-addr grow down from 0x100000 (kernel).
+ */
+ status = "disabled";
+ enable-method = "spin-table";
+
cpu at 0 {
+ device-type = "cpu";
compatible = "sri-cambridge,beri";
+
+ reg = <0>;
+ status = "okay";
};
+
+/*
+ cpu at 1 {
+ device-type = "cpu";
+ compatible = "sri-cambridge,beri";
+
+ reg = <1>;
+ // XXX: should we need cached prefix?
+ cpu-release-addr = <0xffffffff 0x800fffe0>;
+ };
+*/
};
soc {
@@ -74,6 +102,20 @@
reg = <0x0 0x4000000>; // 64M at 0x0
};
+ beripic: beripic at 7f804000 {
+ compatible = "sri-cambridge,beri-pic";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x7f804000 0x400
+ 0x7f806000 0x10
+ 0x7f806080 0x10
+ 0x7f806100 0x10>;
+ interrupts = <0 1 2 3 4>;
+ hard-interrupt-sources = <64>;
+ soft-interrupt-sources = <64>;
+ };
+
display at 4000000 {
compatible = "sri-cambridge,avgen";
reg = <0x4000000 0x1000000>;
@@ -92,10 +134,20 @@
sri-cambridge,devname = "touch";
};
+ serial at 7f002100 {
+ compatible = "ns16550";
+ reg = <0x7f002100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <50000000>;
+ interrupts = <6>;
+ interrupt-parent = <&beripic>;
+ };
+
serial at 7f000000 {
compatible = "altera,jtag_uart-11_0";
reg = <0x7f000000 0x40>;
interrupts = <0>;
+ interrupt-parent = <&beripic>;
};
serial at 7f001000 {
@@ -120,7 +172,28 @@
ethernet at 7f007000 {
compatible = "altera,atse";
- reg = <0x7f007000 0x540>;
+ // MAC, RX+RXC, TX+TXC.
+ reg = <0x7f007000 0x400
+ 0x7f007500 0x8
+ 0x7f007520 0x20
+ 0x7f007400 0x8
+ 0x7f007420 0x20>;
+ // RX, TX
+ interrupts = <1 2>;
+ interrupt-parent = <&beripic>;
+ };
+
+ ethernet at 7f005000 {
+ compatible = "altera,atse";
+ // MAC, RX+RXC, TX+TXC.
+ reg = <0x7f005000 0x400
+ 0x7f005500 0x8
+ 0x7f005520 0x20
+ 0x7f005400 0x8
+ 0x7f005420 0x20>;
+ // RX, TX
+ interrupts = <11 12>;
+ interrupt-parent = <&beripic>;
};
avgen at 0x7f00a000 {
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