PERFORCE change 206887 for review

[Robert Watson]

http://p4web.freebsd.org/@@206887?ac=10

Change 206887 by rwatson at rwatson_svr_ctsrd_mipsbuild on 2012/02/25 21:10:40

	Re-enable use of 'sync' on non-SMP CPUs -- CHERI now supports 'sync'.
	In principle, 'sync' is a 'nop' on UP MIPS CPUs -- and on CHERI, it
	definitely is.

Affected files ...

.. //depot/projects/ctsrd/beribsd/src/sys/mips/include/atomic.h#3 edit
.. //depot/projects/ctsrd/beribsd/src/sys/mips/mips/cache_mipsNN.c#3 edit
.. //depot/projects/ctsrd/beribsd/src/sys/mips/mips/exception.S#3 edit
.. //depot/projects/ctsrd/beribsd/src/sys/mips/mips/swtch.S#3 edit

Differences ...

==== //depot/projects/ctsrd/beribsd/src/sys/mips/include/atomic.h#3 (text+ko) ====

@@ -49,9 +49,7 @@
 mips_sync(void)
 {
 	__asm __volatile (".set noreorder\n\t"
-#ifdef SMP
 			"sync\n\t"
-#endif
 			"nop\n\t"
 			"nop\n\t"
 			"nop\n\t"

==== //depot/projects/ctsrd/beribsd/src/sys/mips/mips/cache_mipsNN.c#3 (text+ko) ====

@@ -72,7 +72,6 @@
 }
 #endif
 
-#ifdef SMP
 #if defined(SB1250_PASS1)
 #define	SYNC	__asm volatile("sync; sync")
 #elif defined(CPU_NLM)
@@ -80,9 +79,6 @@
 #else
 #define	SYNC	__asm volatile("sync")
 #endif
-#else
-#define	SYNC
-#endif
 
 #if defined(CPU_CNMIPS)
 #define SYNCI  mips_sync_icache();

==== //depot/projects/ctsrd/beribsd/src/sys/mips/mips/exception.S#3 (text+ko) ====

@@ -387,9 +387,7 @@
 	or	a1, a1, a0
 	SAVE_REG(a1, SR, sp)
 	RESTORE_CPU			# v0 contains the return address.
-#ifdef SMP
 	sync
-#endif
 	eret
 	.set	at
 END(MipsKernGenException)
@@ -555,9 +553,7 @@
 
 	mtc0	k0, MIPS_COP_0_STATUS	# still exception level
 	ITLBNOPFIX
-#ifdef SMP
 	sync
-#endif
 	eret
 	.set	at
 END(MipsUserGenException)
@@ -649,9 +645,7 @@
 	SAVE_REG(a1, SR, sp)
 	REG_L	v0, CALLFRAME_RA + KERN_REG_SIZE(sp)
 	RESTORE_CPU			# v0 contains the return address.
-#ifdef SMP
 	sync
-#endif
 	eret
 	.set	at
 END(MipsKernIntr)
@@ -826,9 +820,7 @@
 
 	mtc0	k0, MIPS_COP_0_STATUS	# SR with EXL set. 
 	ITLBNOPFIX
-#ifdef SMP
 	sync
-#endif
 	eret
 	.set	at
 END(MipsUserIntr)

==== //depot/projects/ctsrd/beribsd/src/sys/mips/mips/swtch.S#3 (text+ko) ====

@@ -160,9 +160,7 @@
 	or	k0, k0, k1
 	mtc0	k0, MIPS_COP_0_STATUS	# switch to user mode (when eret...)
 	HAZARD_DELAY
-#ifdef SMP
 	sync
-#endif
 	eret
 	.set	at
 END(fork_trampoline)