PERFORCE change 219887 for review
Robert Watson
rwatson at FreeBSD.org
Wed Dec 5 19:46:21 UTC 2012
http://p4web.freebsd.org/@@219887?ac=10
Change 219887 by rwatson at rwatson_svr_ctsrd_mipsbuild on 2012/12/05 19:46:16
Merge an additional change from Mike Roe's GNU assembler support
for CHERI ISAv2:
commit c5f6f3cb5dfaa08de554deaa0236499fbc1fb860
Author: Michael Roe <mroe at cornstalk.org.uk>
Date: Tue Oct 30 13:54:32 2012 +0000
Added assembler support for immediate offsets with the store
operations.
Affected files ...
.. //depot/projects/ctsrd/cheribsd/src/contrib/binutils/gas/config/tc-mips.c#5 edit
.. //depot/projects/ctsrd/cheribsd/src/contrib/binutils/include/opcode/mips.h#3 edit
.. //depot/projects/ctsrd/cheribsd/src/contrib/binutils/opcodes/mips-dis.c#4 edit
.. //depot/projects/ctsrd/cheribsd/src/contrib/binutils/opcodes/mips-opc.c#10 edit
Differences ...
==== //depot/projects/ctsrd/cheribsd/src/contrib/binutils/gas/config/tc-mips.c#5 (text+ko) ====
@@ -8424,6 +8424,7 @@
case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
case 'I': break;
case 'o': USE_BITS (OP_MASK_CDELTA, OP_SH_CDELTA); break;
+ case 'O': USE_BITS (OP_MASK_CDELTA2, OP_SH_CDELTA2); break;
case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
@@ -9216,6 +9217,14 @@
s = expr_end;
continue;
+ case 'O':
+ my_getExpression (&imm_expr, s);
+ check_absolute_expr (ip, &imm_expr);
+ INSERT_OPERAND (CDELTA2, *ip, imm_expr.X_add_number);
+ imm_expr.X_op = O_absent;
+ s = expr_end;
+ continue;
+
case 'T': /* Coprocessor register. */
/* +T is for disassembly only; never match. */
break;
==== //depot/projects/ctsrd/cheribsd/src/contrib/binutils/include/opcode/mips.h#3 (text+ko) ====
@@ -104,6 +104,8 @@
#define OP_SH_DELTA 0
#define OP_MASK_CDELTA 0x7ff
#define OP_SH_CDELTA 0
+#define OP_MASK_CDELTA2 0xff
+#define OP_SH_CDELTA2 3
#define OP_MASK_FUNCT 0x3f
#define OP_SH_FUNCT 0
#define OP_MASK_SPEC 0x3f
@@ -310,10 +312,11 @@
"+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
Requires that "+A" or "+E" occur first to set position.
Enforces: 32 < (pos+size) <= 64.
+ "+O" 8 bit signed offset (OP_*_CDELTA2)
"+w" 5 bit source or destination capability register (OP_*_RT)
"+b" 5 bit source or target capability register (OP_*_RD)
"+v" 5 bit target capability register (OP_*_FD)
- "+o" 11 bit unsigned offset (OP_*_CDELTA)
+ "+o" 11 bit signed offset (OP_*_CDELTA)
Floating point instructions:
"D" 5 bit destination register (OP_*_FD)
==== //depot/projects/ctsrd/cheribsd/src/contrib/binutils/opcodes/mips-dis.c#4 (text+ko) ====
@@ -918,11 +918,17 @@
(*info->fprintf_func) (info->stream, "c%d", (l >> OP_SH_RS) &
OP_MASK_RS);
break;
+
case 'o':
delta = ((l >> OP_SH_CDELTA) & OP_MASK_CDELTA);
(*info->fprintf_func) (info->stream, "%d", delta);
break;
+ case 'O':
+ delta = ((l >> OP_SH_CDELTA2) & OP_MASK_CDELTA2);
+ (*info->fprintf_func) (info->stream, "%d", delta);
+ break;
+
default:
/* xgettext:c-format */
(*info->fprintf_func) (info->stream,
==== //depot/projects/ctsrd/cheribsd/src/contrib/binutils/opcodes/mips-opc.c#10 (text+ko) ====
@@ -188,71 +188,85 @@
{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */
{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */
{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */
-{"cgetperm","t,+b", 0x48000000, 0xffe007ff, 0, 0, I1},
-{"cgettype","t,+b", 0x48000001, 0xffe007ff, 0, 0, I1},
-{"cgetbase","t,+b", 0x48000002, 0xffe007ff, 0, 0, I1},
-{"cgetlen", "t,+b", 0x48000003, 0xffe007ff, 0, 0, I1},
-{"cgetcause", "t", 0x48000004, 0xffe0ffff, 0, 0, I1},
-{"cgettag", "t,+b", 0x48000005, 0xffe007ff, 0, 0, I1},
-{"cgetunsealed", "t,+b", 0x48000006, 0xffe007ff, 0, 0, I1},
-{"cgetpcc", "t(+b)", 0x48000007, 0xffe007ff, 0, 0, I1},
-{"candperm","+w,+b,m", 0x48800000, 0xffe0003f, 0, 0, I1},
-{"csettype","+w,+b,m", 0x48800001, 0xffe0003f, 0, 0, I1},
-{"cincbase","+w,+b,m", 0x48800002, 0xffe0003f, 0, 0, I1},
-{"cmove", "+w,+b", 0x48800002, 0xffe007ff, 0, 0, I1},
-{"csetlen", "+w,+b,m", 0x48800003, 0xffe0003f, 0, 0, I1},
-{"ccleartag", "+w", 0x48800005, 0xffe0ffff, 0, 0, I1},
-{"csc", "+x,d,+o(+w)", 0xf8000000, 0xfc000000, 0, 0, I1},
-{"clc", "+x,d,+o(+w)", 0xd8000000, 0xfc000000, 0, 0, I1},
-{"cscr", "+x,d(+w)", 0xf8000000, 0xfc0007ff, 0, 0, I1},
-{"clcr", "+x,d(+w)", 0xd8000000, 0xfc0007ff, 0, 0, I1},
-{"csci", "+x,+o(+w)", 0xf8000000, 0xfc00f800, 0, 0, I1},
-{"clci", "+x,+o(+w)", 0xd8000000, 0xfc00f800, 0, 0, I1},
-/* mask should be 0xfc000007. Because I don't have letters for the
- * other register and offset argument, temporarily mask them.
- * Hence mask of 0xfc0007ff.
- */
-{"clbu", "v,d(+w)", 0xc8000000, 0xfc0007ff, 0, 0, I1},
-{"clhu", "v,d(+w)", 0xc8000001, 0xfc0007ff, 0, 0, I1},
-{"clwu", "v,d(+w)", 0xc8000002, 0xfc0007ff, 0, 0, I1},
+{"cgetperm", "t,+b", 0x48000000, 0xffe007ff, 0, 0, I1},
+{"cgettype", "t,+b", 0x48000001, 0xffe007ff, 0, 0, I1},
+{"cgetbase", "t,+b", 0x48000002, 0xffe007ff, 0, 0, I1},
+{"cgetlen", "t,+b", 0x48000003, 0xffe007ff, 0, 0, I1},
+{"cgetcause", "t", 0x48000004, 0xffe0ffff, 0, 0, I1},
+{"cgettag", "t,+b", 0x48000005, 0xffe007ff, 0, 0, I1},
+{"cgetunsealed", "t,+b", 0x48000006, 0xffe007ff, 0, 0, I1},
+{"cgetpcc", "t(+b)", 0x48000007, 0xffe007ff, 0, 0, I1},
+{"candperm", "+w,+b,m", 0x48800000, 0xffe0003f, 0, 0, I1},
+{"csettype", "+w,+b,m", 0x48800001, 0xffe0003f, 0, 0, I1},
+{"cincbase", "+w,+b,m", 0x48800002, 0xffe0003f, 0, 0, I1},
+{"cmove", "+w,+b", 0x48800002, 0xffe007ff, 0, 0, I1},
+{"csetlen", "+w,+b,m", 0x48800003, 0xffe0003f, 0, 0, I1},
+{"ccleartag", "+w", 0x48800005, 0xffe0ffff, 0, 0, I1},
+{"csc", "+x,d,+o(+w)", 0xf8000000, 0xfc000000, 0, 0, I1},
+{"clc", "+x,d,+o(+w)", 0xd8000000, 0xfc000000, 0, 0, I1},
+{"cscr", "+x,d(+w)", 0xf8000000, 0xfc0007ff, 0, 0, I1},
+{"clcr", "+x,d(+w)", 0xd8000000, 0xfc0007ff, 0, 0, I1},
+{"csci", "+x,+o(+w)", 0xf8000000, 0xfc00f800, 0, 0, I1},
+{"clci", "+x,+o(+w)", 0xd8000000, 0xfc00f800, 0, 0, I1},
+{"clbu", "v,d,+O(+w)", 0xc8000000, 0xfc000007, 0, 0, I1},
+{"clhu", "v,d,+O(+w)", 0xc8000001, 0xfc000007, 0, 0, I1},
+{"clwu", "v,d,+O(+w)", 0xc8000002, 0xfc000007, 0, 0, I1},
/* there is no cldu */
-{"clb", "v,d(+w)", 0xc8000004, 0xfc0007ff, 0, 0, I1},
-{"clh", "v,d(+w)", 0xc8000005, 0xfc0007ff, 0, 0, I1},
-{"clw", "v,d(+w)", 0xc8000006, 0xfc0007ff, 0, 0, I1},
-{"cld", "v,d(+w)", 0xc8000007, 0xfc0007ff, 0, 0, I1},
+{"clb", "v,d,+O(+w)", 0xc8000004, 0xfc000007, 0, 0, I1},
+{"clh", "v,d,+O(+w)", 0xc8000005, 0xfc000007, 0, 0, I1},
+{"clw", "v,d,+O(+w)", 0xc8000006, 0xfc000007, 0, 0, I1},
+{"cld", "v,d,+O(+w)", 0xc8000007, 0xfc000007, 0, 0, I1},
+{"clbur", "v,d(+w)", 0xc8000000, 0xfc0007ff, 0, 0, I1},
+{"clhur", "v,d(+w)", 0xc8000001, 0xfc0007ff, 0, 0, I1},
+{"clwur", "v,d(+w)", 0xc8000002, 0xfc0007ff, 0, 0, I1},
+/* there is no cldur */
+{"clbr", "v,d(+w)", 0xc8000004, 0xfc0007ff, 0, 0, I1},
+{"clhr", "v,d(+w)", 0xc8000005, 0xfc0007ff, 0, 0, I1},
+{"clwr", "v,d(+w)", 0xc8000006, 0xfc0007ff, 0, 0, I1},
+{"cldr", "v,d(+w)", 0xc8000007, 0xfc0007ff, 0, 0, I1},
+{"clbui", "v,+O(+w)", 0xc8000000, 0xfc00f807, 0, 0, I1},
+{"clhui", "v,+O(+w)", 0xc8000001, 0xfc00f807, 0, 0, I1},
+{"clwui", "v,+O(+w)", 0xc8000002, 0xfc00f807, 0, 0, I1},
+/* there is no cldui */
+{"clbi", "v,+O(+w)", 0xc8000004, 0xfc00f807, 0, 0, I1},
+{"clhi", "v,+O(+w)", 0xc8000005, 0xfc00f807, 0, 0, I1},
+{"clwi", "v,+O(+w)", 0xc8000006, 0xfc00f807, 0, 0, I1},
+{"cldi", "v,+O(+w)", 0xc8000007, 0xfc00f807, 0, 0, I1},
+
+{"csbh", "v,d,+O(+w)", 0xe8000000, 0xfc000007, 0, 0, I1},
+{"cshh", "v,d,+O(+w)", 0xe8000001, 0xfc000007, 0, 0, I1},
+{"cswh", "v,d,+O(+w)", 0xe8000002, 0xfc000007, 0, 0, I1},
+/* there is no csdh */
+{"csb", "v,d,+O(+w)", 0xe8000004, 0xfc000007, 0, 0, I1},
+{"csh", "v,d,+O(+w)", 0xe8000005, 0xfc000007, 0, 0, I1},
+{"csw", "v,d,+O(+w)", 0xe8000006, 0xfc000007, 0, 0, I1},
+{"csd", "v,d,+O(+w)", 0xe8000007, 0xfc000007, 0, 0, I1},
+
+{"csbhr", "v,d(+w)", 0xe8000000, 0xfc0007ff, 0, 0, I1},
+{"cshhr", "v,d(+w)", 0xe8000001, 0xfc0007ff, 0, 0, I1},
+{"cswhr", "v,d(+w)", 0xe8000002, 0xfc0007ff, 0, 0, I1},
+/* there is no csdhr */
+{"csbr", "v,d(+w)", 0xe8000004, 0xfc0007ff, 0, 0, I1},
+{"cshr", "v,d(+w)", 0xe8000005, 0xfc0007ff, 0, 0, I1},
+{"cswr", "v,d(+w)", 0xe8000006, 0xfc0007ff, 0, 0, I1},
+{"csdr", "v,d(+w)", 0xe8000007, 0xfc0007ff, 0, 0, I1},
-{"csbh", "v,d(+w)", 0xe8000000, 0xfc0007ff, 0, 0, I1},
-{"cshh", "v,d(+w)", 0xe8000001, 0xfc0007ff, 0, 0, I1},
-{"cswh", "v,d(+w)", 0xe8000002, 0xfc0007ff, 0, 0, I1},
-/* there is no csdu */
-{"csb", "v,d(+w)", 0xe8000004, 0xfc0007ff, 0, 0, I1},
-{"csh", "v,d(+w)", 0xe8000005, 0xfc0007ff, 0, 0, I1},
-{"csw", "v,d(+w)", 0xe8000006, 0xfc0007ff, 0, 0, I1},
-{"csd", "v,d(+w)", 0xe8000007, 0xfc0007ff, 0, 0, I1},
+{"csbhi", "v,+O(+w)", 0xe8000000, 0xfc00f807, 0, 0, I1},
+{"cshhi", "v,+O(+w)", 0xe8000001, 0xfc00f807, 0, 0, I1},
+{"cswhi", "v,+O(+w)", 0xe8000002, 0xfc00f807, 0, 0, I1},
+/* there is no csdhi */
+{"csbi", "v,+O(+w)", 0xe8000004, 0xfc00f807, 0, 0, I1},
+{"cshi", "v,+O(+w)", 0xe8000005, 0xfc00f807, 0, 0, I1},
+{"cswi", "v,+O(+w)", 0xe8000006, 0xfc00f807, 0, 0, I1},
+{"csdi", "v,+O(+w)", 0xe8000007, 0xfc00f807, 0, 0, I1},
-{"clbi", "t,+o(+b)", 0x4a000000, 0xffe00000,0, 0, I1 },
-{"clhi", "t,+o(+b)", 0x4a200000, 0xffe00000, 0, 0, I1 },
-{"clwi", "t,+o(+b)", 0x4a400000, 0xffe00000, 0, 0, I1 },
-{"cldi", "t,+o(+b)", 0x4a600000, 0xffe00000, 0, 0, I1 },
-{"clbr", "t,m(+b)", 0x4a800000, 0xffe0003f, 0, 0, I1 },
-{"clhr", "t,m(+b)", 0x4aa00000, 0xffe0003f, 0, 0, I1 },
-{"clwr", "t,m(+b)", 0x4ac00000, 0xffe0003f, 0, 0, I1 },
-{"cldr", "t,m(+b)", 0x4ae00000, 0xffe0003f, 0, 0, I1 },
-{"csbi", "t,+o(+b)", 0x4b000000, 0xffe00000, 0, 0, I1 },
-{"cshi", "t,+o(+b)", 0x4b200000, 0xffe00000, 0, 0, I1 },
-{"cswi", "t,+o(+b)", 0x4b400000, 0xffe00000, 0, 0, I1 },
-{"csdi", "t,+o(+b)", 0x4b600000, 0xffe00000, 0, 0, I1 },
-{"csbr", "t,m(+b)", 0x4b800000, 0xffe0003f, 0, 0, I1 },
-{"cshr", "t,m(+b)", 0x4ba00000, 0xffe0003f, 0, 0, I1 },
-{"cswr", "t,m(+b)", 0x4bc00000, 0xffe0003f, 0, 0, I1 },
-{"csdr", "t,m(+b)", 0x4be00000, 0xffe0003f, 0, 0, I1 },
-{"cjr", "m(+b)", 0x49000000, 0xffff003f, 0, 0, I1 },
-{"cjalr", "m(+b)", 0x48e00000, 0xffff003f, 0, 0, I1 },
-{"csealcode","+w,+b", 0x48200000, 0xffe007ff, 0, 0, I1 },
-{"csealdata","+w,+b,+v",0x48400000, 0xffe0003f, 0, 0, I1 },
-{"cunseal", "+w,+b,+v", 0x48600000, 0xffe0003f, 0, 0, I1 },
-{"ccall", "+w,+b", 0x48a00000, 0xffe007ff, 0, 0, I1 },
-{"creturn", "", 0x48c00000, 0xffffffff, 0, 0, I1 },
+{"cjr", "m(+b)", 0x49000000, 0xffff003f, 0, 0, I1},
+{"cjalr", "m(+b)", 0x48e00000, 0xffff003f, 0, 0, I1},
+{"csealcode", "+w,+b", 0x48200000, 0xffe007ff, 0, 0, I1},
+{"csealdata", "+w,+b,+v", 0x48400000, 0xffe0003f, 0, 0, I1},
+{"cunseal", "+w,+b,+v", 0x48600000, 0xffe0003f, 0, 0, I1},
+{"ccall", "+w,+b", 0x48a00000, 0xffe007ff, 0, 0, I1},
+{"creturn", "", 0x48c00000, 0xffffffff, 0, 0, I1},
{"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */
{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */
{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/
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