PERFORCE change 185081 for review
John Baldwin
jhb at FreeBSD.org
Mon Oct 25 15:13:33 UTC 2010
http://p4web.freebsd.org/@@185081?ac=10
Change 185081 by jhb at jhb_jhbbsd on 2010/10/25 15:12:29
- Use intr_disable/intr_restore instead of frobbing the flags
register directly.
- Use 'saveintr' instead of 'savecrit' or 'eflags' to hold the
state returned by 'intr_disable'.
Affected files ...
.. //depot/projects/smpng/sys/amd64/amd64/fpu.c#18 edit
.. //depot/projects/smpng/sys/amd64/include/profile.h#11 edit
.. //depot/projects/smpng/sys/i386/i386/elan-mmcr.c#27 edit
.. //depot/projects/smpng/sys/i386/i386/identcpu.c#71 edit
.. //depot/projects/smpng/sys/i386/i386/initcpu.c#38 edit
.. //depot/projects/smpng/sys/i386/i386/longrun.c#5 edit
.. //depot/projects/smpng/sys/i386/i386/perfmon.c#15 edit
.. //depot/projects/smpng/sys/i386/include/profile.h#17 edit
.. //depot/projects/smpng/sys/i386/isa/npx.c#71 edit
.. //depot/projects/smpng/sys/x86/x86/local_apic.c#6 edit
Differences ...
==== //depot/projects/smpng/sys/amd64/amd64/fpu.c#18 (text+ko) ====
@@ -113,14 +113,14 @@
void
fpuinit(void)
{
- register_t savecrit;
+ register_t saveintr;
u_int mxcsr;
u_short control;
/*
* It is too early for critical_enter() to work on AP.
*/
- savecrit = intr_disable();
+ saveintr = intr_disable();
stop_emulating();
fninit();
control = __INITIAL_FPUCW__;
@@ -137,7 +137,7 @@
bzero(fpu_initialstate.sv_xmm, sizeof(fpu_initialstate.sv_xmm));
}
start_emulating();
- intr_restore(savecrit);
+ intr_restore(saveintr);
}
/*
==== //depot/projects/smpng/sys/amd64/include/profile.h#11 (text+ko) ====
@@ -77,17 +77,17 @@
#error this file needs to be ported to your compiler
#endif /* !__GNUCLIKE_ASM */
#else /* !GUPROF */
-#define MCOUNT_DECL(s) u_long s;
+#define MCOUNT_DECL(s) register_t s;
#ifdef SMP
extern int mcount_lock;
-#define MCOUNT_ENTER(s) { s = read_rflags(); disable_intr(); \
+#define MCOUNT_ENTER(s) { s = intr_disable(); \
while (!atomic_cmpset_acq_int(&mcount_lock, 0, 1)) \
/* nothing */ ; }
#define MCOUNT_EXIT(s) { atomic_store_rel_int(&mcount_lock, 0); \
- write_rflags(s); }
+ intr_restore(s); }
#else
-#define MCOUNT_ENTER(s) { s = read_rflags(); disable_intr(); }
-#define MCOUNT_EXIT(s) (write_rflags(s))
+#define MCOUNT_ENTER(s) { s = intr_disable(); }
+#define MCOUNT_EXIT(s) (intr_restore(s))
#endif
#endif /* GUPROF */
==== //depot/projects/smpng/sys/i386/i386/elan-mmcr.c#27 (text+ko) ====
@@ -228,19 +228,18 @@
static int state;
int i;
uint16_t u, x, y, z;
- u_long eflags;
+ register_t saveintr;
/*
* Grab the HW state as quickly and compactly as we can. Disable
* interrupts to avoid measuring our interrupt service time on
* hw with quality clock sources.
*/
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
x = *pps_ap[0]; /* state, must be first, see below */
y = *pps_ap[1]; /* timer2 */
z = *pps_ap[2]; /* timer1 */
- write_eflags(eflags);
+ intr_restore(saveintr);
/*
* Order is important here. We need to check the state of the GPIO
==== //depot/projects/smpng/sys/i386/i386/identcpu.c#71 (text+ko) ====
@@ -1037,12 +1037,11 @@
static void
identifycyrix(void)
{
- u_int eflags;
+ register_t saveintr;
int ccr2_test = 0, dir_test = 0;
u_char ccr2, ccr3;
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
ccr2 = read_cyrix_reg(CCR2);
write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
@@ -1067,7 +1066,7 @@
else
cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
- write_eflags(eflags);
+ intr_restore(saveintr);
}
/* Update TSC freq with the value indicated by the caller. */
==== //depot/projects/smpng/sys/i386/i386/initcpu.c#38 (text+ko) ====
@@ -116,14 +116,13 @@
static void
init_bluelightning(void)
{
- u_long eflags;
+ register_t saveintr;
#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
need_post_dma_flush = 1;
#endif
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
load_cr0(rcr0() | CR0_CD | CR0_NW);
invd();
@@ -144,7 +143,7 @@
/* Enable caching in CR0. */
load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
invd();
- write_eflags(eflags);
+ intr_restore(saveintr);
}
/*
@@ -153,11 +152,10 @@
static void
init_486dlc(void)
{
- u_long eflags;
+ register_t saveintr;
u_char ccr0;
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
invd();
ccr0 = read_cyrix_reg(CCR0);
@@ -189,7 +187,7 @@
load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
invd();
#endif /* !CYRIX_CACHE_WORKS */
- write_eflags(eflags);
+ intr_restore(saveintr);
}
@@ -199,11 +197,10 @@
static void
init_cy486dx(void)
{
- u_long eflags;
+ register_t saveintr;
u_char ccr2;
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
invd();
ccr2 = read_cyrix_reg(CCR2);
@@ -220,7 +217,7 @@
#endif
write_cyrix_reg(CCR2, ccr2);
- write_eflags(eflags);
+ intr_restore(saveintr);
}
@@ -230,11 +227,10 @@
static void
init_5x86(void)
{
- u_long eflags;
+ register_t saveintr;
u_char ccr2, ccr3, ccr4, pcr0;
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
load_cr0(rcr0() | CR0_CD | CR0_NW);
wbinvd();
@@ -320,29 +316,28 @@
/* Lock NW bit in CR0. */
write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
- write_eflags(eflags);
+ intr_restore(saveintr);
}
#ifdef CPU_I486_ON_386
/*
* There are i486 based upgrade products for i386 machines.
- * In this case, BIOS doesn't enables CPU cache.
+ * In this case, BIOS doesn't enable CPU cache.
*/
static void
init_i486_on_386(void)
{
- u_long eflags;
+ register_t saveintr;
#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
need_post_dma_flush = 1;
#endif
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
- write_eflags(eflags);
+ intr_restore(saveintr);
}
#endif
@@ -354,11 +349,10 @@
static void
init_6x86(void)
{
- u_long eflags;
+ register_t saveintr;
u_char ccr3, ccr4;
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
load_cr0(rcr0() | CR0_CD | CR0_NW);
wbinvd();
@@ -422,7 +416,7 @@
/* Lock NW bit in CR0. */
write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
- write_eflags(eflags);
+ intr_restore(saveintr);
}
#endif /* I486_CPU */
@@ -435,11 +429,10 @@
static void
init_6x86MX(void)
{
- u_long eflags;
+ register_t saveintr;
u_char ccr3, ccr4;
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
load_cr0(rcr0() | CR0_CD | CR0_NW);
wbinvd();
@@ -489,7 +482,7 @@
/* Lock NW bit in CR0. */
write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
- write_eflags(eflags);
+ intr_restore(saveintr);
}
static void
@@ -513,11 +506,10 @@
init_mendocino(void)
{
#ifdef CPU_PPRO2CELERON
- u_long eflags;
+ register_t saveintr;
u_int64_t bbl_cr_ctl3;
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
load_cr0(rcr0() | CR0_CD | CR0_NW);
wbinvd();
@@ -541,7 +533,7 @@
}
load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
- write_eflags(eflags);
+ intr_restore(saveintr);
#endif /* CPU_PPRO2CELERON */
}
@@ -795,14 +787,14 @@
enable_K5_wt_alloc(void)
{
u_int64_t msr;
- register_t savecrit;
+ register_t saveintr;
/*
* Write allocate is supported only on models 1, 2, and 3, with
* a stepping of 4 or greater.
*/
if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
- savecrit = intr_disable();
+ saveintr = intr_disable();
msr = rdmsr(0x83); /* HWCR */
wrmsr(0x83, msr & !(0x10));
@@ -833,7 +825,7 @@
msr=rdmsr(0x83);
wrmsr(0x83, msr|0x10); /* enable write allocate */
- intr_restore(savecrit);
+ intr_restore(saveintr);
}
}
@@ -842,10 +834,9 @@
{
quad_t size;
u_int64_t whcr;
- u_long eflags;
+ register_t saveintr;
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
wbinvd();
#ifdef CPU_DISABLE_CACHE
@@ -895,7 +886,7 @@
#endif
wrmsr(0x0c0000082, whcr);
- write_eflags(eflags);
+ intr_restore(saveintr);
}
void
@@ -903,10 +894,9 @@
{
quad_t size;
u_int64_t whcr;
- u_long eflags;
+ register_t saveintr;
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
wbinvd();
#ifdef CPU_DISABLE_CACHE
@@ -956,7 +946,7 @@
#endif
wrmsr(0x0c0000082, whcr);
- write_eflags(eflags);
+ intr_restore(saveintr);
}
#endif /* I585_CPU && CPU_WT_ALLOC */
@@ -966,15 +956,14 @@
DB_SHOW_COMMAND(cyrixreg, cyrixreg)
{
- u_long eflags;
+ register_t saveintr;
u_int cr0;
u_char ccr1, ccr2, ccr3;
u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
cr0 = rcr0();
if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
@@ -992,7 +981,7 @@
pcr0 = read_cyrix_reg(PCR0);
write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
}
- write_eflags(eflags);
+ intr_restore(saveintr);
if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
printf("CCR0=%x, ", (u_int)ccr0);
==== //depot/projects/smpng/sys/i386/i386/longrun.c#5 (text+ko) ====
@@ -84,12 +84,11 @@
static u_int
tmx86_get_longrun_mode(void)
{
- u_long eflags;
+ register_t saveintr;
union msrinfo msrinfo;
u_int low, high, flags, mode;
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
@@ -105,40 +104,38 @@
}
mode = LONGRUN_MODE_UNKNOWN;
out:
- write_eflags(eflags);
+ intr_restore(saveintr);
return (mode);
}
static u_int
tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
{
- u_long eflags;
+ register_t saveintr;
u_int regs[4];
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
do_cpuid(0x80860007, regs);
*frequency = regs[0];
*voltage = regs[1];
*percentage = regs[2];
- write_eflags(eflags);
+ intr_restore(saveintr);
return (1);
}
static u_int
tmx86_set_longrun_mode(u_int mode)
{
- u_long eflags;
+ register_t saveintr;
union msrinfo msrinfo;
if (mode >= LONGRUN_MODE_UNKNOWN) {
return (0);
}
- eflags = read_eflags();
- disable_intr();
+ saveintr = intr_disable();
/* Write LongRun mode values to Model Specific Register. */
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
@@ -153,7 +150,7 @@
msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
- write_eflags(eflags);
+ intr_restore(saveintr);
return (1);
}
==== //depot/projects/smpng/sys/i386/i386/perfmon.c#15 (text+ko) ====
@@ -128,18 +128,18 @@
int
perfmon_setup(int pmc, unsigned int control)
{
- register_t savecrit;
+ register_t saveintr;
if (pmc < 0 || pmc >= NPMC)
return EINVAL;
perfmon_inuse |= (1 << pmc);
control &= ~(PMCF_SYS_FLAGS << 16);
- savecrit = intr_disable();
+ saveintr = intr_disable();
ctl_shadow[pmc] = control;
writectl(pmc);
wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
- intr_restore(savecrit);
+ intr_restore(saveintr);
return 0;
}
@@ -174,17 +174,17 @@
int
perfmon_start(int pmc)
{
- register_t savecrit;
+ register_t saveintr;
if (pmc < 0 || pmc >= NPMC)
return EINVAL;
if (perfmon_inuse & (1 << pmc)) {
- savecrit = intr_disable();
+ saveintr = intr_disable();
ctl_shadow[pmc] |= (PMCF_EN << 16);
wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
writectl(pmc);
- intr_restore(savecrit);
+ intr_restore(saveintr);
return 0;
}
return EBUSY;
@@ -193,17 +193,17 @@
int
perfmon_stop(int pmc)
{
- register_t savecrit;
+ register_t saveintr;
if (pmc < 0 || pmc >= NPMC)
return EINVAL;
if (perfmon_inuse & (1 << pmc)) {
- savecrit = intr_disable();
+ saveintr = intr_disable();
pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
ctl_shadow[pmc] &= ~(PMCF_EN << 16);
writectl(pmc);
- intr_restore(savecrit);
+ intr_restore(saveintr);
return 0;
}
return EBUSY;
==== //depot/projects/smpng/sys/i386/include/profile.h#17 (text+ko) ====
@@ -77,17 +77,17 @@
#error
#endif /* !__GNUCLIKE_ASM */
#else /* !GUPROF */
-#define MCOUNT_DECL(s) u_long s;
+#define MCOUNT_DECL(s) register_t s;
#ifdef SMP
extern int mcount_lock;
-#define MCOUNT_ENTER(s) { s = read_eflags(); disable_intr(); \
+#define MCOUNT_ENTER(s) { s = intr_disable(); \
while (!atomic_cmpset_acq_int(&mcount_lock, 0, 1)) \
/* nothing */ ; }
#define MCOUNT_EXIT(s) { atomic_store_rel_int(&mcount_lock, 0); \
- write_eflags(s); }
+ intr_restore(s); }
#else
-#define MCOUNT_ENTER(s) { s = read_eflags(); disable_intr(); }
-#define MCOUNT_EXIT(s) (write_eflags(s))
+#define MCOUNT_ENTER(s) { s = intr_disable(); }
+#define MCOUNT_EXIT(s) (intr_restore(s))
#endif
#endif /* GUPROF */
==== //depot/projects/smpng/sys/i386/isa/npx.c#71 (text+ko) ====
@@ -343,7 +343,7 @@
npxinit(void)
{
static union savefpu dummy;
- register_t savecrit;
+ register_t saveintr;
u_short control;
if (!hw_float)
@@ -355,7 +355,7 @@
*
* It is too early for critical_enter() to work on AP.
*/
- savecrit = intr_disable();
+ saveintr = intr_disable();
npxsave(&dummy);
stop_emulating();
#ifdef CPU_ENABLE_SSE
@@ -366,7 +366,7 @@
control = __INITIAL_NPXCW__;
fldcw(control);
start_emulating();
- intr_restore(savecrit);
+ intr_restore(saveintr);
}
/*
==== //depot/projects/smpng/sys/x86/x86/local_apic.c#6 (text+ko) ====
@@ -341,12 +341,12 @@
{
struct lapic *la;
u_int32_t maxlvt;
- register_t eflags;
+ register_t saveintr;
char buf[MAXCOMLEN + 1];
la = &lapics[lapic_id()];
KASSERT(la->la_present, ("missing APIC structure"));
- eflags = intr_disable();
+ saveintr = intr_disable();
maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
/* Initialize the TPR to allow all interrupts. */
@@ -393,7 +393,7 @@
if (maxlvt >= LVT_CMCI)
lapic->lvt_cmci = lvt_mode(la, LVT_CMCI, lapic->lvt_cmci);
- intr_restore(eflags);
+ intr_restore(saveintr);
}
void
@@ -1415,7 +1415,7 @@
void
lapic_ipi_raw(register_t icrlo, u_int dest)
{
- register_t value, eflags;
+ register_t value, saveintr;
/* XXX: Need more sanity checking of icrlo? */
KASSERT(lapic != NULL, ("%s called too early", __func__));
@@ -1425,7 +1425,7 @@
("%s: reserved bits set in ICR LO register", __func__));
/* Set destination in ICR HI register if it is being used. */
- eflags = intr_disable();
+ saveintr = intr_disable();
if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
value = lapic->icr_hi;
value &= ~APIC_ID_MASK;
@@ -1438,7 +1438,7 @@
value &= APIC_ICRLO_RESV_MASK;
value |= icrlo;
lapic->icr_lo = value;
- intr_restore(eflags);
+ intr_restore(saveintr);
}
#define BEFORE_SPIN 1000000
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