PERFORCE change 158117 for review
Arnar Mar Sig
antab at FreeBSD.org
Mon Feb 23 06:31:22 PST 2009
http://perforce.freebsd.org/chv.cgi?CH=158117
Change 158117 by antab at antab_farm on 2009/02/23 14:31:15
Get ddb/kdb working
Affected files ...
.. //depot/projects/avr32/src/sys/avr32/avr32/cpu.c#6 edit
.. //depot/projects/avr32/src/sys/avr32/avr32/db_disasm.c#3 edit
.. //depot/projects/avr32/src/sys/avr32/avr32/db_interface.c#4 edit
.. //depot/projects/avr32/src/sys/avr32/avr32/db_trace.c#2 edit
.. //depot/projects/avr32/src/sys/avr32/avr32/exception.S#5 edit
.. //depot/projects/avr32/src/sys/avr32/avr32/machdep.c#7 edit
.. //depot/projects/avr32/src/sys/avr32/avr32/pmap.c#6 edit
.. //depot/projects/avr32/src/sys/avr32/avr32/support.S#5 edit
.. //depot/projects/avr32/src/sys/avr32/avr32/switch.S#5 edit
.. //depot/projects/avr32/src/sys/avr32/avr32/trap.c#5 edit
.. //depot/projects/avr32/src/sys/avr32/avr32/vm_machdep.c#6 edit
.. //depot/projects/avr32/src/sys/avr32/include/asm.h#2 edit
.. //depot/projects/avr32/src/sys/avr32/include/db_disasm.h#1 add
.. //depot/projects/avr32/src/sys/avr32/include/db_machdep.h#4 edit
Differences ...
==== //depot/projects/avr32/src/sys/avr32/avr32/cpu.c#6 (text+ko) ====
@@ -73,7 +73,7 @@
sysreg_write(EVBA, (uint32_t)&_evba);
__asm__ __volatile__ ("csrf %0" : : "i"(AT32_SYS_SR_EM));
-#if 0 // defined(DDB)
+#if defined(DDB)
/*
* Enable Debug mode in monitor mode. Allow peripherals to run
* while in debug mode so we can report tru uart.
==== //depot/projects/avr32/src/sys/avr32/avr32/db_disasm.c#3 (text+ko) ====
@@ -34,15 +34,1083 @@
#include <vm/vm.h>
#include <vm/pmap.h>
-
#include <ddb/ddb.h>
#include <ddb/db_output.h>
#include <machine/db_machdep.h>
-#include <machine/debug.h>
+#include <machine/db_disasm.h>
+
+static void avr32_reglist16_output(avr32_inst_t);
+
+/*
+ * Branch instruction conditions
+ */
+static char *avr32_cond[] = {
+ "eq", "ne", "cc", "cs",
+ "ge", "lt", "mi", "pl",
+ "ls", "gt", "le", "hi",
+ "vs", "vc", "qs", "al"
+};
+
+/**
+ * Reglist8
+ */
+static char *avr32_reglist8[] = {
+ "r0-r3", "r4-r7", "r8-r9", "r10",
+ "r11", "r12", "lr", "pc"
+};
+
+/**
+ * Reglist16
+ */
+static char *avr32_reglist16[] = {
+ "r0", "r1", "r2", "r3",
+ "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11",
+ "r12", "sp", "lr", "pc"
+};
+
+/**
+ * Halfword select
+ */
+static char *avr32_halfword_sel[] = {
+ "b", "t"
+};
+
+/**
+ * Byte select
+ */
+static char *avr32_byte_sel[] = {
+ "b", "l", "u", "t"
+};
+
+/**
+ * Co-processor double list
+ */
+static char *avr32_cr_double[] = {
+ "cr0-cr1", "cr2-cr3", "cr4-cr5", "cr6-cr7",
+ "cr8-cr9", "cr10-cr11", "cr12-cr13", "cr14-cr15"
+};
+
+/**
+ * Co-processor high list
+ */
+static char *avr32_cr_high[] = {
+ "cr8", "cr9", "cr10", "cr11",
+ "cr12", "cr13", "cr14", "cr15"
+};
+
+/**
+ * Co-procesor low list
+ */
+static char *avr32_cr_low[] = {
+ "cr0", "cr1", "cr2", "cr3",
+ "cr4", "cr5", "cr6", "cr7"
+};
+
+static struct avr32_inst_info avr32_instructions[] = {
+ { "abs", 2, 0xFFF00000, 0x5C400000, avr32_inst_1reg, },
+ { "acall", 2, 0xF00F0000, 0xD0000000, avr32_inst_k8 },
+ { "acr", 2, 0xFFF00000, 0x5C000000, avr32_inst_1reg },
+ { "adc", 4, 0xE1F0FFF0, 0xE0000040, avr32_inst_3reg },
+ { "add", 2, 0xE1F00000, 0x00000000, avr32_inst_2reg },
+ { "add", 4, 0xE1F0FFC0, 0xE0000000, avr32_inst_3reg_2shift, INST_SHIFT_LEFT },
+ { "add", 4, 0xE1F0F0F0, 0xE1D0E000, avr32_inst_3reg, 0, avr32_inst_cond4, 8 },
+ { "addabs", 4, 0xE1F0FFF0, 0xE0000E40, avr32_inst_3reg },
+ { "addhh.w", 4, 0xE1F0FFC0, 0XE0000E00, avr32_inst_dsp_hw },
+ { "and", 2, 0xE1F00000, 0x00600000, avr32_inst_2reg },
+ { "and", 4, 0xE1F0FE00, 0xE1E00000, avr32_inst_3reg_5shift, INST_SHIFT_LEFT },
+ { "and", 4, 0xE1F0FE00, 0xE1E00200, avr32_inst_3reg_5shift, INST_SHIFT_RIGHT },
+ { "and", 4, 0xE1F0F0F0, 0xE1D0E020, avr32_inst_3reg, 0, avr32_inst_cond4, 8 },
+ { "andh", 4, 0xFDF00000, 0xE4100000, avr32_inst_andlh },
+ { "andl", 4, 0xFDF00000, 0xE0100000, avr32_inst_andlh },
+ { "andn", 2, 0xE1F00000, 0x00800000, avr32_inst_2reg },
+ { "asr", 4, 0xE1F0FFF0, 0xE0000840, avr32_inst_3reg },
+ { "asr", 2, 0xE1E00000, 0xA1400000, avr32_inst_1reg_5bit },
+ { "asr", 4, 0xE1F0FFE0, 0xE0001400, avr32_inst_2reg_k5 },
+ { "bfexts", 4, 0xE1F0FC00, 0xE1D0B000, avr32_inst_2reg_2k5 },
+ { "bfextu", 4, 0xE1F0FC00, 0xE1D0C000, avr32_inst_2reg_2k5 },
+ { "bfins", 4, 0xE1F0FC00, 0xE1D0D000, avr32_inst_2reg_2k5 },
+ { "bld", 4, 0xFFF0FFE0, 0xEDB00000, avr32_inst_1reg_5bite },
+ { "br", 2, 0xF0080000, 0xC0000000, avr32_inst_disp8, 0, avr32_inst_cond3 },
+ { "br", 4, 0xE1E00000, 0xE0800000, avr32_inst_disp21, 0, avr32_inst_cond4, 16 },
+ { "breakpoint", 2, 0xFFFF0000, 0xD6730000, },
+ { "brev", 2, 0xFFF00000, 0x5C900000, avr32_inst_1reg },
+ { "bst", 4, 0xFFF0FFE0, 0xEFB00000, avr32_inst_1reg_5bite },
+ { "cache", 4, 0xFFF00000, 0xF4100000, avr32_inst_cache },
+ { "casts.h", 2, 0xFFF00000, 0x5C800000, avr32_inst_1reg },
+ { "casts.b", 2, 0xFFF00000, 0x5C600000, avr32_inst_1reg },
+ { "castu.h", 2, 0xFFF00000, 0x5C800000, avr32_inst_1reg },
+ { "castu.b", 2, 0xFFF00000, 0x5C500000, avr32_inst_1reg },
+ { "cbr", 2, 0xE1E00000, 0xA1C00000, avr32_inst_1reg_5bit },
+ { "clz", 4, 0xE1F0FFFF, 0xE0001200, avr32_inst_2reg },
+ { "com", 2, 0xFFF00000, 0x5CD00000, avr32_inst_1reg },
+ { "cop", 4, 0xF9F00000, 0xE1A00000, avr32_inst_co_op },
+ { "cp.b", 4, 0xE1F0FFFF, 0xE0001800, avr32_inst_2reg },
+ { "cp.h", 4, 0xE1F0FFFF, 0xE0001900, avr32_inst_2reg },
+ { "cp.w", 2, 0xE1F00000, 0x00300000, avr32_inst_2reg },
+ { "cp.w", 2, 0xFC000000, 0x58000000, avr32_inst_1reg_k6 },
+ { "cp.w", 4, 0xE1E00000, 0xE0400000, avr32_inst_1reg_imm21 },
+ { "cpc", 4, 0xE1F0FFFF, 0xE0001300, avr32_inst_2reg },
+ { "cpc", 2, 0xFFF00000, 0x5C200000, avr32_inst_1reg },
+ { "csrf", 2, 0xFE0F0000, 0xD4030000, avr32_inst_sreg },
+ { "csrfcz", 2, 0xFE0F0000, 0xD0030000, avr32_inst_sreg },
+ { "divs", 4, 0xE1F0FFC0, 0xE0000C00, avr32_inst_3reg },
+ { "divu", 4, 0xE1F0FFC0, 0xE0000D00, avr32_inst_3reg },
+ { "eor", 2, 0xE1F00000, 0x00500000, avr32_inst_2reg },
+ { "eor", 4, 0xE1F0FE00, 0xE1E02000, avr32_inst_3reg_5shift, INST_SHIFT_LEFT },
+ { "eor", 4, 0xE1F0FE00, 0xE1E02200, avr32_inst_3reg_5shift, INST_SHIFT_RIGHT },
+ { "eor", 4, 0xE1F0F0F0, 0xE1D0E040, avr32_inst_3reg, 0, avr32_inst_cond4, 8 },
+ { "eorh", 4, 0xFFF00000, 0xEE100000, avr32_inst_1reg_k16 },
+ { "eorl", 4, 0xFFF00000, 0xEC100000, avr32_inst_1reg_k16 },
+ { "frs", 2, 0xFFFF0000, 0xD7430000, },
+ { "icall", 2, 0xFFF00000, 0x5D100000, avr32_inst_1reg },
+ { "incjosp", 2, 0xFF8F0000, 0xD6830000, avr32_inst_imm3 },
+ { "ld.d", 2, 0xE1F10000, 0xA1010000, avr32_inst_2reg, INST_PTR2_INC },
+ { "ld.d", 2, 0xE1F10000, 0xA1100000, avr32_inst_2reg, INST_PTR2_DEC },
+ { "ld.d", 2, 0xE1F10000, 0xA1000000, avr32_inst_2reg },
+ { "ld.d", 4, 0xE1F10000, 0xE0E00000, avr32_inst_2reg_disp16_load },
+ { "ld.d", 4, 0xE1F0FFC1, 0xE0000200, avr32_inst_3reg_disp_2shift_load },
+ { "ld.sb", 4, 0xE1F00000, 0xE1200000, avr32_inst_2reg_disp16_load },
+ { "ld.sb", 4, 0xE1F0FFC0, 0xE0000600, avr32_inst_3reg_disp_2shift_load },
+ { "ld.sb", 4, 0xE1F00E00, 0xE1F00600, avr32_inst_2reg_disp9_load, 0, avr32_inst_cond4, 12 },
+ { "ld.ub", 2, 0xE1F00000, 0x01300000, avr32_inst_2reg, INST_PTR2_INC },
+ { "ld.ub", 2, 0xE1F00000, 0x01700000, avr32_inst_2reg, INST_PTR2_DEC },
+ { "ld.ub", 2, 0xE1800000, 0x01800000, avr32_inst_2reg_disp3_load, 0 },
+ { "ld.ub", 4, 0xE1F00000, 0xE1300000, avr32_inst_2reg_disp16_load },
+ { "ld.ub", 4, 0xE1F0FFC0, 0xE0000700, avr32_inst_3reg_disp_2shift_load },
+ { "ld.ub", 4, 0XE1F00E00, 0xE1F00800, avr32_inst_2reg_disp9_load, 0, avr32_inst_cond4, 12 },
+ { "ld.sh", 2, 0xE1F00000, 0x01100000, avr32_inst_2reg, INST_PTR2_INC },
+ { "ld.sh", 2, 0xE1F00000, 0x01500000, avr32_inst_2reg, INST_PTR2_DEC },
+ { "ld.sh", 2, 0xE1800000, 0x80000000, avr32_inst_2reg_disp3_load, 1 },
+ { "ld.sh", 4, 0xE1F00000, 0xE1000000, avr32_inst_2reg_disp16_load },
+ { "ld.sh", 4, 0xE1F0FFC0, 0xE0000400, avr32_inst_3reg_disp_2shift_load },
+ { "ld.sh", 4, 0xE1F00E00, 0xE1F00200, avr32_inst_2reg_disp9_load, 1, avr32_inst_cond4, 12 },
+ { "ld.uh", 2, 0xE1F00000, 0x01200000, avr32_inst_2reg, INST_PTR2_INC },
+ { "ld.uh", 2, 0xE1F00000, 0x01600000, avr32_inst_2reg, INST_PTR2_DEC },
+ { "ld.uh", 2, 0xE1800000, 0x80800000, avr32_inst_2reg_disp3_load, 1 },
+ { "ld.uh", 4, 0xE1F00000, 0xE1100000, avr32_inst_2reg_disp16_load },
+ { "ld.uh", 4, 0xE1F0FFC0, 0xE0000500, avr32_inst_3reg_disp_2shift_load },
+ { "ld.uh", 4, 0xE1F00E00, 0xE1F00400, avr32_inst_2reg_disp9_load, 1, avr32_inst_cond4, 12 },
+ { "ld.w", 2, 0xE1F00000, 0x01000000, avr32_inst_2reg, INST_PTR2_INC },
+ { "ld.w", 2, 0xE1F00000, 0x01400000, avr32_inst_2reg, INST_PTR2_DEC },
+ { "ld.w", 2, 0xE0000000, 0x60000000, avr32_inst_2reg_disp3_load, 2 },
+ { "ld.w", 4, 0xE1F00000, 0xE0F00000, avr32_inst_2reg_disp16_load },
+ { "ld.w", 4, 0xE1F0FFC0, 0xE0000300, avr32_inst_3reg_disp_2shift_load },
+ { "ld.w", 4, 0xE1F0FFC0, 0xE0000F80, avr32_inst_2reg_disp_part_load },
+ { "ld.w", 4, 0xE1F00E00, 0xE1F00000, avr32_inst_2reg_disp9_load, 2, avr32_inst_cond4, 12 },
+ { "ldc.d", 4, 0xFFF01100, 0xE9A01000, avr32_inst_co_disp8_load },
+ { "ldc.d", 4, 0xFFF011FF, 0xEFA00050, avr32_inst_co_load },
+ { "ldc.d", 4, 0xFFF011C0, 0xEFA01040, avr32_inst_co_disp_2shift_load },
+ { "ldc.w", 4, 0xFFF01000, 0xE9A00000, avr32_inst_co_disp8_load },
+ { "ldc.w", 4, 0xFFF010FF, 0xEFA00040, avr32_inst_co_load },
+ { "ldc.w", 4, 0xFFF010C0, 0xEFA01000, avr32_inst_co_disp_2shift_load },
+ { "ldc0.d", 4, 0xFFF00100, 0xF3A00000, avr32_inst_co0_load },
+ { "ldc0.w", 4, 0XFFF00000, 0xF1A00000, avr32_inst_co0_load },
+ { "ldcm.d", 4, 0xFFF00F00, 0xEDA00400, avr32_inst_co_load_many, (int)avr32_cr_double },
+ { "ldcm.w", 4, 0xFFF00F00, 0xEDA00100, avr32_inst_co_load_many, (int)avr32_cr_high },
+ { "ldcm.w", 4, 0xFFF00F00, 0xEDA00000, avr32_inst_co_load_many, (int)avr32_cr_low },
+ { "lddpc", 2, 0xF8000000, 0x48000000, avr32_inst_rel_load },
+ { "lddsp", 2, 0xF8000000, 0x40000000, avr32_inst_rel_load },
+ { "ldins.b", 4, 0xE1F0C000, 0xE1D04000, avr32_inst_2reg_k12_byte },
+ { "ldins.h", 4, 0xE1F0E000, 0xE1D00000, avr32_inst_2reg_k12_halfword },
+ { "ldm", 4, 0xFDF00000, 0xE1C00000, avr32_inst_load_many },
+ { "ldmts", 4, 0xFDF00000, 0xE5C00000, avr32_inst_load_many },
+ { "ldswp.sh", 4, 0xE1F0F000, 0xE1D02000, avr32_inst_2reg_disp12_load, 1 },
+ { "ldswp.uh", 4, 0xE1F0F000, 0xE1D03000, avr32_inst_2reg_disp12_load, 1 },
+ { "ldswp.w", 4, 0xE1F0F000, 0xE1D08000, avr32_inst_2reg_disp12_load, 2 },
+ { "lsl", 4, 0xE1F0FFF0, 0xE0000940, avr32_inst_3reg },
+ { "lsl", 2, 0xE1E00000, 0xA1600000, avr32_inst_1reg_5bit },
+ { "lsl", 4, 0xE1F0FFE0, 0xE0001500, avr32_inst_2reg_k5, },
+ { "lsr", 4, 0xE1F0FFF0, 0xE0000A40, avr32_inst_3reg },
+ { "lsr", 2, 0xE1E00000, 0xA1800000, avr32_inst_1reg_5bit },
+ { "lsr", 4, 0XE1F0FFE0, 0xE0001600, avr32_inst_2reg_k5, },
+ { "mac", 4, 0xE1F0FFF0, 0xE0000340, avr32_inst_3reg },
+ { "machh.d", 4, 0xE1F0FFC0, 0xE0000580, avr32_inst_dsp_hw },
+ { "machh.w", 4, 0xE1F0FFC0, 0xE0000480, avr32_inst_dsp_hw },
+ { "macs.d", 4, 0xE1F0FFF0, 0xE0000540, avr32_inst_3reg },
+ { "macsathh.w", 4, 0xE1F0FFC0, 0xE0000680, avr32_inst_dsp_hw },
+ { "macu.d", 4, 0xE1F0FFF0, 0xE0000740, avr32_inst_3reg },
+ { "macwh.d", 4, 0xE1F0FFE0, 0xE0000C80, avr32_inst_dsp_w },
+ { "max", 4, 0xE1F0FFF0, 0xE0000C40, avr32_inst_3reg },
+ { "mcall", 4, 0xFFF00000, 0xF0100000, avr32_inst_1reg_disp16s2 },
+ { "memc", 4, 0xFFF00000, 0xF6100000, avr32_inst_addr15_b5 },
+ { "mems", 4, 0xFFF00000, 0xF8100000, avr32_inst_addr15_b5 },
+ { "memt", 4, 0xFFF00000, 0xFA100000, avr32_inst_addr15_b5 },
+ { "mfdr", 4, 0xFFF0FF00, 0xE5B00000, avr32_inst_st_reg },
+ { "mfsr", 4, 0xFFF0FF00, 0xE1B00000, avr32_inst_st_reg },
+ { "min", 4, 0xE1F0FFF0, 0xE0000D40, avr32_inst_3reg },
+ { "mov", 2, 0xF0000000, 0x30000000, avr32_inst_1reg_imm8 },
+ { "mov", 4, 0xE1E00000, 0xE0600000, avr32_inst_1reg_imm21 },
+ { "mov", 2, 0xE1F00000, 0x00900000, avr32_inst_2reg },
+ { "mov", 4, 0xE1F0FF0F, 0xE0001700, avr32_inst_2reg, 0, avr32_inst_cond4, 4 },
+ { "mov", 4, 0xFFF0F000, 0xF9B00000, avr32_inst_1reg_imm8_ext , 0, avr32_inst_cond4, 8 },
+ { "movhi", 4, 0xFFF00000, 0xFC100000, avr32_inst_1reg_k16 },
+ { "mtdr", 4, 0xFFF0FF00, 0xE7B00000, avr32_inst_reg_st },
+ { "mtsr", 4, 0xFFF0FF00, 0xE3B00000, avr32_inst_reg_st },
+ { "mul", 2, 0xE1F00000, 0xA1300000, avr32_inst_2reg },
+ { "mul", 4, 0xE1F0FFF0, 0xE0000240, avr32_inst_3reg },
+ { "mul", 4, 0xE1F0FF00, 0xE0001000, avr32_inst_2reg_imm8 },
+ { "mulhh.w", 4, 0xE1F0FFC0, 0xE0000780, avr32_inst_dsp_hw },
+ { "mulnhh.w", 4, 0xE1F0FFC0, 0xE0000180, avr32_inst_dsp_hw },
+ { "mulnwh.d", 4, 0xE1F0FFE1, 0xE0000280, avr32_inst_dsp_w },
+ { "muls.d", 4, 0xE1F0FFF0, 0xE0000440, avr32_inst_3reg },
+ { "mulsathh.h", 4, 0xE1F0FFC0, 0xE0000880, avr32_inst_dsp_hw },
+ { "mulsathh.w", 4, 0xE1F0FFC0, 0xE0000980, avr32_inst_dsp_hw },
+ { "mulsatrndhh.h", 4, 0xE1F0FFC0, 0xE0000A80, avr32_inst_dsp_hw },
+ { "mulsatrndwh.h", 4, 0xE1F0FFE0, 0xE0000B80, avr32_inst_dsp_w },
+ { "mulsatwh.w", 4, 0xE1F0FFE0, 0xE0000E80, avr32_inst_dsp_w },
+ { "mulu.d", 4, 0xE1F0FFF0, 0xE0000640, avr32_inst_3reg },
+ { "mulwh.d", 4, 0xE1F0FFE0, 0xE0000D80, avr32_inst_dsp_w },
+ { "musfr", 2, 0xFFF00000, 0x5D300000, avr32_inst_1reg },
+ { "mustr", 2, 0xFFF00000, 0x5D200000, avr32_inst_1reg },
+ { "mvcr.d", 4, 0xFFF111FF, 0xEFA00010, avr32_inst_co_to_reg },
+ { "mvcr.w", 4, 0xFFF010FF, 0xEFA00000, avr32_inst_co_to_reg },
+ { "mvrc.d", 4, 0xFFF111FF, 0xEFA00030, avr32_inst_reg_to_co },
+ { "mvrc.w", 4, 0xFFF010FF, 0xEFA00020, avr32_inst_reg_to_co },
+ { "neg", 2, 0xFFF00000, 0x5C300000, avr32_inst_1reg },
+ { "nop", 2, 0xFFFF0000, 0xD7030000, },
+ { "or", 2, 0xE1F00000, 0x00400000, avr32_inst_2reg },
+ { "or", 4, 0xE1F0FE00, 0xE1E01000, avr32_inst_3reg_5shift, INST_SHIFT_LEFT },
+ { "or", 4, 0xE1F0FE00, 0xE1E01200, avr32_inst_3reg_5shift, INST_SHIFT_RIGHT },
+ { "or", 4, 0xE1F0F0F0, 0xE1D0E030, avr32_inst_3reg, 0, avr32_inst_cond4, 8 },
+ { "orh", 4, 0xFFF00000, 0xEA100000, avr32_inst_1reg_k16 },
+ { "orl", 4, 0xFFF00000, 0xE8100000, avr32_inst_1reg_k16 },
+ { "pabs.sb", 4, 0xFFF0FFF0, 0xE00023E0, avr32_inst_2reg_ext },
+ { "pabs.sh", 4, 0xFFF0FFF0, 0xE00023F0, avr32_inst_2reg_ext },
+ { "packsh.ub", 4, 0xE1F0FFF0, 0xE00024C0, avr32_inst_3reg },
+ { "packsh.sb", 4, 0xE1F0FFF0, 0xE00024D0, avr32_inst_3reg },
+ { "packw.sh", 4, 0xE1F0FFF0, 0xE0002470, avr32_inst_3reg },
+ { "padd.b", 4, 0xE1F0FFF0, 0xE0002300, avr32_inst_3reg },
+ { "padd.h", 4, 0xE1F0FFF0, 0xE0002000, avr32_inst_3reg },
+ { "paddh.ub", 4, 0xE1F0FFF0, 0xE0002360, avr32_inst_3reg },
+ { "paddh.sh", 4, 0xE1F0FFF0, 0xE00020C0, avr32_inst_3reg },
+ { "padds.ub", 4, 0xE1F0FFF0, 0xE0002340, avr32_inst_3reg },
+ { "padds.sb", 4, 0xE1F0FFF0, 0xE0002320, avr32_inst_3reg },
+ { "padds.uh", 4, 0xE1F0FFF0, 0xE0002080, avr32_inst_3reg },
+ { "padds.sh", 4, 0xE1F0FFF0, 0xe0002040, avr32_inst_3reg },
+ { "paddsub.h", 4, 0xE1F0FFC0, 0xE0002100, avr32_inst_dsp_hw },
+ { "paddsubh.sh",4, 0xE1F0FFC0, 0xE0002280, avr32_inst_dsp_hw },
+ { "paddsubs.uh",4, 0xE1F0FFC0, 0xE0002200, avr32_inst_dsp_hw },
+ { "paddsubs.sh",4, 0xE1F0FFC0, 0xE0002180, avr32_inst_dsp_hw },
+ { "paddx.h", 4, 0xE1F0FFF0, 0xE0002020, avr32_inst_3reg },
+ { "paddxh.sh", 4, 0xE1F0FFF0, 0xE00020E0, avr32_inst_3reg },
+ { "paddxs.uh", 4, 0xE1F0FFF0, 0xE00020A0, avr32_inst_3reg },
+ { "paddxs.sh", 4, 0xE1F0FFF0, 0xE0002060, avr32_inst_3reg },
+ { "pasr.b", 4, 0xE1F8FFF0, 0xE0002410, avr32_inst_2reg_k3 },
+ { "pasr.h", 4, 0xE1F0FFF0, 0xE0002440, avr32_inst_2reg_k4 },
+ { "pavg.ub", 4, 0xE1F0FFF0, 0xE00023C0, avr32_inst_3reg },
+ { "pavg.sh", 4, 0xE1F0FFF0, 0xE00023D0, avr32_inst_3reg },
+ { "plsl.b", 4, 0xE1F8FFF0, 0xE0002420, avr32_inst_2reg_k3 },
+ { "plsl.h", 4, 0xE1F0FFF0, 0xE0002450, avr32_inst_2reg_k4 },
+ { "plsr.b", 4, 0xE1F8FFF0, 0xE0002430, avr32_inst_2reg_k3 },
+ { "plsr.h", 4, 0xE1F0FFF0, 0xE0002460, avr32_inst_2reg_k4 },
+ { "pmax.ub", 4, 0xE1F0FFF0, 0xE0002380, avr32_inst_3reg },
+ { "pmax.sh", 4, 0xE1F0FFF0, 0xE0002390, avr32_inst_3reg },
+ { "pmin.ub", 4, 0xE1F0FFF0, 0xE00023A0, avr32_inst_3reg },
+ { "pmin.sh", 4, 0xE1F0FFF0, 0xE00023B0, avr32_inst_3reg },
+ { "popjc", 2, 0xFFFF0000, 0xD7130000, },
+ { "popm", 2, 0xF0070000, 0xD0020000, avr32_inst_mreg },
+ { "pref", 4, 0xFFF00000, 0xF2100000, avr32_inst_1reg_disp16 },
+ { "psad", 4, 0xE1F0FFF0, 0xE0002400, avr32_inst_3reg },
+ { "psub.b", 4, 0xE1F0FFF0, 0xE0002310, avr32_inst_3reg },
+ { "psub.h", 4, 0xE1F0FFF0, 0xe0002010, avr32_inst_3reg },
+ { "psubadd.h", 4, 0xE1F0FFC0, 0xE0002140, avr32_inst_dsp_hw },
+ { "psubaddh.sh",4, 0xE1F0FFC0, 0xE00022C0, avr32_inst_dsp_hw },
+ { "psubadds.uh",4, 0xE1F0FFC0, 0xE0002240, avr32_inst_dsp_hw },
+ { "psubadds.sh",4, 0xE1F0FFC0, 0xE00021C0, avr32_inst_dsp_hw },
+ { "psubh.ub", 4, 0xE1F0FFF0, 0xE0002370, avr32_inst_3reg },
+ { "psubh.sh", 4, 0xE1F0FFF0, 0xE00020D0, avr32_inst_3reg },
+ { "psubs.ub", 4, 0xE1F0FFF0, 0xE0002350, avr32_inst_3reg },
+ { "psubs.sb", 4, 0xE1F0FFF0, 0xE0002330, avr32_inst_3reg },
+ { "psubs.uh", 4, 0xE1F0FFF0, 0xe0002090, avr32_inst_3reg },
+ { "psbus.sh", 4, 0xE1F0FFF0, 0xE0002050, avr32_inst_3reg },
+ { "psubx.h", 4, 0xE1F0FFF0, 0xE0002030, avr32_inst_3reg },
+ { "psubxh.sh", 4, 0xE1F0FFF0, 0xE00020F0, avr32_inst_3reg },
+ { "psubxs.uh", 4, 0xE1F0FFF0, 0xE00020B0, avr32_inst_3reg },
+ { "psubxs.sh", 4, 0xE1F0FFF0, 0xE0002070, avr32_inst_3reg },
+ { "punpcksb.h", 4, 0xE1FFFFE0, 0xE00024A0, avr32_inst_2reg_sel },
+ { "punpckub.h", 4, 0xE1FFFFE0, 0xE0002480, avr32_inst_2reg_sel },
+ { "pushjc", 2, 0xFFFF0000, 0xD7230000, },
+ { "pushm", 2, 0xF00F0000, 0xD0010000, avr32_inst_mreg },
+ { "rcall", 2, 0xF00C0000, 0xC00C0000, avr32_inst_disp10 },
+ { "rcall", 4, 0xE1EF0000, 0xE0A00000, avr32_inst_k21 },
+ { "ret", 2, 0xFF000000, 0x5E000000, avr32_inst_1reg, 0, avr32_inst_cond4, 20 },
+ { "retd", 2, 0xFFFF0000, 0xD6230000, },
+ { "rete", 2, 0xFFFF0000, 0xD6030000, },
+ { "retj", 2, 0xFFFF0000, 0xD6330000, },
+ { "rets", 2, 0xFFFF0000, 0xD6130000, },
+ { "rjmp", 2, 0xF00C0000, 0xC0080000, avr32_inst_disp10 },
+ { "rol", 2, 0xFFF00000, 0x5CF00000, avr32_inst_1reg },
+ { "ror", 2, 0xFFF00000, 0x5D000000, avr32_inst_1reg },
+ { "rsub", 2, 0xE1F00000, 0x00200000, avr32_inst_2reg },
+ { "rsub", 4, 0xE1F0FF00, 0xE0001100, avr32_inst_2reg_imm8 },
+ { "rsub", 4, 0xFFF0F000, 0xFBB00000, avr32_inst_1reg_imm8_ext, 0, avr32_inst_cond4, 8 },
+ { "satadd.h", 4, 0xE1F0FFF0, 0xE00002C0, avr32_inst_3reg },
+ { "satadd.w", 4, 0xE1F0FFF0, 0xE00000C0, avr32_inst_3reg },
+ { "satrnds", 4, 0xFFF0FC00, 0xF3B00000, avr32_inst_saturate },
+ { "satrndu", 4, 0xFFF0FC00, 0xF3B00400, avr32_inst_saturate },
+ { "sats", 4, 0xFFF0FC00, 0xF1B00000, avr32_inst_saturate },
+ { "satsub.h", 4, 0xE1F0FFF0, 0xE00003C0, avr32_inst_3reg },
+ { "satsub.w", 4, 0xE1F0FFF0, 0xE00001C0, avr32_inst_3reg },
+ { "satsub.w", 4, 0xE1F00000, 0xE0D00000, avr32_inst_2reg_imm16 },
+ { "satu", 4, 0xFFF0FC00, 0xF1B00400, avr32_inst_saturate },
+ { "sbc", 4, 0xE1F0FFF0, 0xE0000140, avr32_inst_3reg },
+ { "sbr", 2, 0xE1E00000, 0xA1A00000, avr32_inst_1reg_5bit },
+ { "scall", 2, 0xFFFF0000, 0xD7330000, },
+ { "scr", 2, 0xFFF00000, 0x5C100000, avr32_inst_1reg },
+ { "sleep", 4, 0xFFFFFF00, 0xE9B00000, avr32_inst_ss },
+ { "sr", 2, 0xFF000000, 0x5F000000, avr32_inst_1reg, 0, avr32_inst_cond4, 20 },
+ { "ssrf", 2, 0xFE0F0000, 0xD2030000, avr32_inst_sreg },
+ { "st.b", 2, 0xE1F00000, 0x00C00000, avr32_inst_2reg, INST_REG_FLIP | INST_PTR1_INC },
+ { "st.b", 2, 0xE1F00000, 0x00F00000, avr32_inst_2reg, INST_REG_FLIP | INST_PTR1_DEC },
+ { "st.b", 2, 0xE1800000, 0xA0800000, avr32_inst_2reg_disp3_store },
+ { "st.b", 4, 0xE1F00000, 0xE1600000, avr32_inst_2reg_disp16_store, },
+ { "st.b", 4, 0xE1F0FFC0, 0xE0000B00, avr32_inst_3reg_disp_2shift_store },
+ { "st.b", 4, 0xE1F00E00, 0xE1F00E00, avr32_inst_2reg_disp9_store, 0, avr32_inst_cond4, 12 },
+ { "st.d", 2, 0xE1F10000, 0xA1200000, avr32_inst_2reg, INST_REG_DOUBLE | INST_REG_FLIP | INST_PTR1_INC },
+ { "st.d", 2, 0xE1F10000, 0xA1210000, avr32_inst_2reg, INST_REG_DOUBLE | INST_REG_FLIP | INST_PTR1_DEC },
+ { "st.d", 2, 0xE1F10000, 0xA1110000, avr32_inst_2reg, INST_REG_DOUBLE | INST_REG_FLIP },
+ { "st.d", 4, 0xE1F10000, 0xE0E10000, avr32_inst_2reg_disp16_store, INST_REG_DOUBLE },
+ { "st.d", 4, 0xE1F0FFC1, 0xE0000800, avr32_inst_3reg_disp_2shift_store, INST_REG_DOUBLE },
+ { "st.h", 2, 0xE1F00000, 0x00B00000, avr32_inst_2reg, INST_REG_FLIP | INST_PTR1_INC },
+ { "st.h", 2, 0xE1F00000, 0x00E00000, avr32_inst_2reg, INST_REG_FLIP | INST_PTR1_DEC },
+ { "st.h", 2, 0xE1800000, 0xA0000000, avr32_inst_2reg_disp3_store, 1 },
+ { "st.h", 4, 0xE1F00000, 0xE1500000, avr32_inst_2reg_disp16_store },
+ { "st.h", 4, 0xE1F0FFC0, 0xE0000A00, avr32_inst_3reg_disp_2shift_store },
+ { "st.h", 4, 0xE1F00E00, 0xE1F00C00, avr32_inst_2reg_disp9_store, 1, avr32_inst_cond4, 12 },
+ { "st.w", 2, 0xE1F00000, 0x00A00000, avr32_inst_2reg, INST_REG_FLIP | INST_PTR1_INC },
+ { "st.w", 2, 0xE1F00000, 0x00D00000, avr32_inst_2reg, INST_REG_FLIP | INST_PTR1_DEC },
+ { "st.w", 2, 0xE1000000, 0x81000000, avr32_inst_2reg_disp4_store, 2 },
+ { "st.w", 4, 0xE1F00000, 0xE1400000, avr32_inst_2reg_disp16_store },
+ { "st.w", 4, 0xE1F0FFC0, 0xE0000900, avr32_inst_3reg_disp_2shift_store },
+ { "st.w", 4, 0xE1F00E00, 0xE1F00A00, avr32_inst_2reg_disp9_store, 2, avr32_inst_cond4, 12 },
+ { "stc.d", 4, 0xFFF01100, 0xEBA01000, avr32_inst_co_disp8_store },
+ { "stc.d", 4, 0xFFF011F0, 0xEFA00070, avr32_inst_co_store, INST_PTR1_INC },
+ { "stc.d", 4, 0xFFF011C0, 0xEFA010C0, avr32_inst_co_disp_2shift_store },
+ { "stc.w", 4, 0xFFF01000, 0xEBA00000, avr32_inst_co_disp8_store },
+ { "stc.w", 4, 0xFFF010FF, 0xEFA00060, avr32_inst_co_store, INST_PTR1_INC },
+ { "stc.w", 4, 0xFFF010C0, 0xEFA01080, avr32_inst_co_disp_2shift_store },
+ { "stc0.d", 4, 0xFFF00000, 0xF7A00000, avr32_inst_co0_store },
+ { "stc0.w", 4, 0xFFF00000, 0xF5A00000, avr32_inst_co0_store },
+ { "stcm.d", 4, 0xFFF00F00, 0xEDA00500, avr32_inst_co_store_many, (int)avr32_cr_double },
+ { "stcm.w", 4, 0xFFF00F00, 0xEDA00300, avr32_inst_co_store_many, (int)avr32_cr_high },
+ { "stcm.w", 4, 0xFFF00F00, 0xEDA00200, avr32_inst_co_store_many, (int)avr32_cr_low },
+ { "stcond", 4, 0xE1F00000, 0xE1700000, avr32_inst_2reg_disp16_store },
+ { "stdsp", 2, 0xF8000000, 0x50000000, avr32_inst_rel_store, 13 },
+ { "sthh.w", 4, 0xE1F0C000, 0xE1E0C000, avr32_inst_3reg_k8 },
+ { "sthh.w", 4, 0xE1F0C0C0, 0xE1E08000, avr32_inst_4reg_k2 },
+ { "stm", 4, 0xFDF00000, 0xE9C00000, avr32_inst_store_many },
+ { "stmts", 4, 0xFDF00000, 0xEDC00000, avr32_inst_store_many },
+ { "stswp.h", 4, 0xE1F0F000, 0xE1D09000, avr32_inst_2reg_disp12_store, 1 },
+ { "stswp.w", 4, 0xE1F0F000, 0xE1D0A000, avr32_inst_2reg_disp12_store, 2 },
+ { "sub", 2, 0xE1F00000, 0x00100000, avr32_inst_2reg },
+ { "sub", 4, 0xE1F0FFC0, 0xE0000100, avr32_inst_3reg_2shift, INST_SHIFT_LEFT },
+ { "sub", 2, 0xF0000000, 0x20000000, avr32_inst_1reg_imm8 },
+ { "sub", 4, 0xE1E00000, 0xE0200000, avr32_inst_1reg_imm21 },
+ { "sub", 4, 0xE1F00000, 0xE0C00000, avr32_inst_2reg_imm16 },
+ { "sub", 4, 0xFDF0F000, 0xF5B00000, avr32_inst_1reg_imm8_ext, 0, avr32_inst_cond4f },
+ { "sub", 4, 0xE1F0F0F0, 0xE1D0E010, avr32_inst_3reg, 0, avr32_inst_cond4, 8 },
+ { "subhh.w", 4, 0xE1F0FFC0, 0xE0000F00, avr32_inst_dsp_hw },
+ { "swap.b", 2, 0xFFF00000, 0x5CB00000, avr32_inst_1reg },
+ { "swap.bh", 2, 0xFFF00000, 0x5CC00000, avr32_inst_1reg },
+ { "swap.h", 2, 0xFFF00000, 0x5CA00000, avr32_inst_1reg },
+ { "sync", 4, 0xFFFFFF00, 0xEBB00000, avr32_inst_ss },
+ { "tlbr", 2, 0xFFFF0000, 0xD6430000, },
+ { "tlbs", 2, 0xFFFF0000, 0xD6530000, },
+ { "tlbw", 2, 0xFFFF0000, 0xD6630000, },
+ { "tnbz", 2, 0xFFF00000, 0x5CE00000, avr32_inst_1reg },
+ { "tst", 2, 0xE1F00000, 0x00700000, avr32_inst_1reg },
+ { "xchg", 4, 0xE1F0FFF0, 0xE0000B40, avr32_inst_3reg },
+ { NULL }
+};
db_addr_t
db_disasm(db_addr_t loc, boolean_t altfmt)
{
- avr32_impl();
- return (0);
+ struct avr32_inst_info *walker;
+ avr32_inst_t inst;
+
+ db_read_bytes(loc, sizeof(avr32_inst_t), (char *)&inst);
+
+ walker = avr32_instructions;
+ while (walker->name) {
+ if (walker->mask != 0 && (inst & walker->mask) == walker->opcode) {
+ goto found;
+ }
+ walker++;
+ }
+ db_printf("UNKNOWN");
+ return (loc + 2);
+
+found:
+ db_printf("%s", walker->name);
+ if (walker->cond != NULL) {
+ walker->cond(inst, walker->cond_arg);
+ }
+ db_printf("\t");
+ if (walker->operand != NULL) {
+ walker->operand(inst, walker->operand_arg);
+ }
+ return (loc + walker->size);
+}
+
+static void
+avr32_reglist16_output(avr32_inst_t inst)
+{
+ int i, set, at;
+
+ for (i = set = at = 0; i < 16; i++) {
+ if (inst & (1 << i)) {
+ if (!at) {
+ if (set) {
+ db_printf(",");
+ }
+ db_printf("%s", avr32_reglist16[i]);
+ set++;
+ at = 0;
+ }
+ at++;
+ }
+ else if (at > 1) {
+ db_printf("-%s", avr32_reglist16[i - 1]);
+ at = 0;
+ }
+ else {
+ at = 0;
+ }
+ }
+ if (at > 1) {
+ db_printf("-pc");
+ }
+}
+
+/*** Only reg */
+AVR32_INST_FORMAT(avr32_inst_1reg) {
+ db_printf("%s", EXTRACT_REG(inst, RY));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg) {
+ char *r1, *r2;
+
+ if (arg & INST_REG_DOUBLE) {
+ inst &= ~ 0x00010000;
+ }
+
+ if (arg & INST_REG_FLIP) {
+ r1 = EXTRACT_REG(inst, RX);
+ r2 = EXTRACT_REG(inst, RY);
+ } else {
+ r1 = EXTRACT_REG(inst, RY);
+ r2 = EXTRACT_REG(inst, RX);
+ }
+
+ if (arg & INST_PTR1_DEC) {
+ db_printf("--");
+ }
+ db_printf("%s", r1);
+ if (arg & INST_PTR1_INC) {
+ db_printf("++");
+ }
+ db_printf(", ");
+ if (arg & INST_PTR2_DEC) {
+ db_printf("--");
+ }
+ db_printf("%s", r2);
+ if (arg & INST_PTR2_INC) {
+ db_printf("++");
+ }
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_ext) {
+ db_printf("%s, %s",
+ EXTRACT_REG(inst, RD),
+ EXTRACT_REG(inst, RY));
+}
+
+AVR32_INST_FORMAT(avr32_inst_3reg) {
+ db_printf("%s, %s, %s",
+ EXTRACT_REG(inst, RD),
+ EXTRACT_REG(inst, RX),
+ EXTRACT_REG(inst, RY));
+}
+
+/*** Reg + K */
+AVR32_INST_FORMAT(avr32_inst_1reg_k6) {
+ db_printf("%s, %d",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_IMM(inst, 6, 20));
+}
+AVR32_INST_FORMAT(avr32_inst_1reg_k16) {
+ db_printf("%s, %d",
+ EXTRACT_REG(inst, RY),
+ EXTRACT(inst, 0x0000FFFF, 0));
+}
+AVR32_INST_FORMAT(avr32_inst_2reg_k3) {
+ db_printf("%s, %s, %d",
+ EXTRACT_REG(inst, RD),
+ EXTRACT_REG(inst, RX),
+ EXTRACT(inst, 0x00070000, 16));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_k4) {
+ db_printf("%s, %s, %d",
+ EXTRACT_REG(inst, RD),
+ EXTRACT_REG(inst, RX),
+ EXTRACT(inst, 0x000F0000, 16));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_k5) {
+ db_printf("%s, %s, %d",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_REG(inst, RX),
+ EXTRACT(inst, 0x0000001F, 0));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_2k5) {
+ db_printf("%s, %s, %d, %d",
+ EXTRACT_REG(inst, RX),
+ EXTRACT_REG(inst, RY),
+ EXTRACT(inst, 0x000003E0, 5),
+ EXTRACT(inst, 0x0000001F, 0));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_k12_byte) {
+ db_printf("%s:%s, %s[%d]",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_BYTE(inst, PART),
+ EXTRACT_REG(inst, RX),
+ EXTRACT(inst, 0x00000FFF, 0));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_k12_halfword) {
+ db_printf("%s:%s, %s[%d]",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_HALFWORD(inst, PART),
+ EXTRACT_REG(inst, RX),
+ EXTRACT(inst, 0x00000FFF, 0) << 1);
+}
+
+AVR32_INST_FORMAT(avr32_inst_3reg_k8) {
+ db_printf("%s[0x%x] %s:%s %s:%s",
+ EXTRACT_REG(inst, RD),
+ EXTRACT(inst, 0x00000FF0, 4) << 2,
+ EXTRACT_REG(inst, RX),
+ EXTRACT_HALFWORD(inst, X),
+ EXTRACT_REG(inst, RY),
+ EXTRACT_HALFWORD(inst, Y));
+}
+
+AVR32_INST_FORMAT(avr32_inst_4reg_k2) {
+ db_printf("%s[%s << %d] %s:%s %s:%s",
+ EXTRACT_REG(inst, RD),
+ EXTRACT_REG(inst, RI),
+ EXTRACT(inst, 0x00000030, 4),
+ EXTRACT_REG(inst, RX),
+ EXTRACT_HALFWORD(inst, X),
+ EXTRACT_REG(inst, RY),
+ EXTRACT_HALFWORD(inst, Y));
+}
+
+/*** Reg + imm */
+AVR32_INST_FORMAT(avr32_inst_1reg_imm8) {
+ db_printf("%s, %d",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_IMM(inst, 8, 20));
+}
+
+AVR32_INST_FORMAT(avr32_inst_1reg_imm8_ext) {
+ db_printf("%s, %d",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_IMM(inst, 8, 0));
+}
+
+AVR32_INST_FORMAT(avr32_inst_1reg_imm21) {
+ db_printf("%s, %d",
+ EXTRACT_REG(inst, RY),
+ SE( ((inst & 0x1E000000) >> 8) |
+ ((inst & 0x00100000) >> 4) |
+ (inst & 0x0000FFFF), 21));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_imm8) {
+ db_printf("%s, %s, %d",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_REG(inst, RX),
+ EXTRACT_IMM(inst, 8, 0));
+}
+
+/*** Reg + disp */
+AVR32_INST_FORMAT(avr32_inst_1reg_disp16) {
+ db_printf("%s[%d]",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_IMM(inst, 16, 0));
+}
+AVR32_INST_FORMAT(avr32_inst_1reg_disp16s2) {
+ db_printf("%s[%d]",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_IMM(inst, 16, 0) << 2);
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_disp_part_load) {
+ db_printf("%s, %s[%s:%s << 2]",
+ EXTRACT_REG(inst, RD),
+ EXTRACT_REG(inst, RX),
+ EXTRACT_REG(inst, RY),
+ EXTRACT_BYTE(inst, XY));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_disp3_load) {
+ db_printf("%s, %s[0x%x]",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_REG(inst, RX),
+ EXTRACT(inst, 0x00700000, 20) << arg);
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_disp3_store) {
+ db_printf("%s[0x%x], %s",
+ EXTRACT_REG(inst, RX),
+ EXTRACT(inst, 0x00700000, 20) << arg,
+ EXTRACT_REG(inst, RY));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_disp4_store) {
+ db_printf("%s[0x%x], %s",
+ EXTRACT_REG(inst, RX),
+ EXTRACT(inst, 0x00F00000, 20) << arg,
+ EXTRACT_REG(inst, RY));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_disp9_load) {
+ db_printf("%s, %s[0x%x]",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_REG(inst, RX),
+ EXTRACT(inst, 0x000001FF, 0) << arg);
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_disp9_store) {
+ db_printf("%s[0x%x], %s",
+ EXTRACT_REG(inst, RX),
+ EXTRACT(inst, 0x000001FF, 0) << arg,
+ EXTRACT_REG(inst, RY));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_disp12_load) {
+ db_printf("%s, %s[%d]",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_REG(inst, RX),
+ EXTRACT_IMM(inst, 12, 0) << arg);
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_disp12_store) {
+ db_printf("%s[%d], %s",
+ EXTRACT_REG(inst, RX),
+ EXTRACT_IMM(inst, 12, 0) << arg,
+ EXTRACT_REG(inst, RY));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_disp16_load) {
+ db_printf("%s, %s[%d]",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_REG(inst, RX),
+ EXTRACT_IMM(inst, 16, 0));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_disp16_store) {
+ if (arg & INST_REG_DOUBLE) {
+ inst &= ~0x00010000;
+ }
+
+ db_printf("%s[%d], %s",
+ EXTRACT_REG(inst, RX),
+ EXTRACT_IMM(inst, 16, 0),
+ EXTRACT_REG(inst, RY));
+}
+
+AVR32_INST_FORMAT(avr32_inst_2reg_imm16) {
+ db_printf("%s, %s, %d",
+ EXTRACT_REG(inst, RY),
+ EXTRACT_REG(inst, RX),
+ EXTRACT_IMM(inst, 16, 0));
+}
+
+
+/*** Reg + shift */
+AVR32_INST_FORMAT(avr32_inst_3reg_2shift) {
+ char *dir;
+
+ if (arg & INST_SHIFT_LEFT) {
+ dir = "<<";
+ } else {
+ dir = ">>";
+ }
+
+ db_printf("%s, %s, %s %s %d",
+ EXTRACT_REG(inst, RD),
+ EXTRACT_REG(inst, RX),
+ EXTRACT_REG(inst, RY),
+ dir,
+ EXTRACT(inst, 0x0000030, 4));
+}
+
+AVR32_INST_FORMAT(avr32_inst_3reg_disp_2shift_load) {
+ db_printf("%s, %s[%s << %d]",
+ EXTRACT_REG(inst, RD),
+ EXTRACT_REG(inst, RX),
+ EXTRACT_REG(inst, RY),
+ EXTRACT(inst, 0x0000030, 4));
+}
+
+AVR32_INST_FORMAT(avr32_inst_3reg_disp_2shift_store) {
+ if (arg & INST_REG_DOUBLE) {
+ inst &= ~0x00010000;
+ }
+
+ db_printf("%s[%s << %d], %s",
+ EXTRACT_REG(inst, RX),
+ EXTRACT_REG(inst, RY),
+ EXTRACT(inst, 0x0000030, 4),
+ EXTRACT_REG(inst, RD));
+}
+
+AVR32_INST_FORMAT(avr32_inst_3reg_5shift) {
+ char *dir;
+
+ if (arg & INST_SHIFT_LEFT) {
+ dir = "<<";
+ } else {
+ dir = ">>";
+ }
+
+ db_printf("%s, %s, %s %s %d",
+ EXTRACT_REG(inst, RD),
+ EXTRACT_REG(inst, RX),
+ EXTRACT_REG(inst, RY),
+ dir,
+ EXTRACT(inst, 0x000001F0, 4));
+}
+
+/*** Reg + bit */
+AVR32_INST_FORMAT(avr32_inst_1reg_5bit) {
+ db_printf("%s, %d",
+ EXTRACT_REG(inst, RY),
+ ((inst >> 24) & 0x1E) | ((inst >> 20) & 0x01));
+}
+
+AVR32_INST_FORMAT(avr32_inst_1reg_5bite) {
+ db_printf("%s, %d",
+ EXTRACT_REG(inst, RY),
+ EXTRACT(inst, 0x0000001F, 0));
+}
+
+/*** DSP */
+AVR32_INST_FORMAT(avr32_inst_dsp_hw) {
+ db_printf("%s, %s:%s, %s:%s",
+ EXTRACT_REG(inst, RD),
+ EXTRACT_REG(inst, RX),
+ EXTRACT_HALFWORD(inst, X),
+ EXTRACT_REG(inst, RY),
+ EXTRACT_HALFWORD(inst, Y));
+}
+
+AVR32_INST_FORMAT(avr32_inst_dsp_w) {
+ db_printf("%s, %s, %s:%s",
+ EXTRACT_REG(inst, RD),
+ EXTRACT_REG(inst, RX),
+ EXTRACT_REG(inst, RY),
+ EXTRACT_HALFWORD(inst, Y));
+}
+
+/*** Only Imm, K or disp */
+AVR32_INST_FORMAT(avr32_inst_imm3) {
+ db_printf("%d", EXTRACT_IMM(inst, 3, 20));
+}
+
+AVR32_INST_FORMAT(avr32_inst_disp8) {
+ db_printf("%d", EXTRACT_IMM(inst, 8, 20) << 1);
+}
+
+AVR32_INST_FORMAT(avr32_inst_disp10) {
+ db_printf("%d",SE(
+ ((inst & 0x0FF00000) >> 20) |
+ ((inst & 0x00030000) >> 8), 10) << 1);
+}
+
+AVR32_INST_FORMAT(avr32_inst_disp21) {
+ db_printf("%d",
+ SE(((inst & 0x1E000000) >> 8) |
+ ((inst & 0x00100000) >> 4) |
+ (inst & 0x0000FFFF), 21) << 1);
+}
+
+AVR32_INST_FORMAT(avr32_inst_k8) {
+ db_printf("0x%x", EXTRACT(inst, 0x0FF00000, 20) << 2);
+}
+
+AVR32_INST_FORMAT(avr32_inst_k21) {
+ db_printf("0x%x",
+ ((inst & 0x1E000000) >> 8) |
+ ((inst & 0x00100000) >> 4) |
+ (inst & 0x0000FFFF));
+}
+
+/*** Co-Processor ops */
+AVR32_INST_FORMAT(avr32_inst_co_op) {
+ db_printf("cp%d, cr%d, cr%d, cr%d, 0x%x",
+ EXTRACT_CP(inst),
+ EXTRACT_CR(inst, CRD),
+ EXTRACT_CR(inst, CRX),
+ EXTRACT_CR(inst, CRY),
+ (inst & 0x06000000) >> 20 |
+ (inst & 0x000F0000) >> 15 |
+ (inst & 0x00001000) >> 12);
+}
+
+AVR32_INST_FORMAT(avr32_inst_co0_load) {
+ db_printf("cr%d, %s[0x%x]",
+ EXTRACT_CR(inst, CRD),
+ EXTRACT_REG(inst, RY),
+ ((inst & 0x0000F000) >> 12 | (inst & 0x000000FF)) << 2);
+}
+
+AVR32_INST_FORMAT(avr32_inst_co0_store) {
+ db_printf("%s[0x%x], cr%d",
+ EXTRACT_REG(inst, RY),
+ ((inst & 0x0000F000) >> 12 | (inst & 0x000000FF)) << 2,
+ EXTRACT_CR(inst, CRD));
+}
+
+AVR32_INST_FORMAT(avr32_inst_co_to_reg) {
+ db_printf("cp%d, %s, cr%d",
+ EXTRACT_CP(inst),
+ EXTRACT_REG(inst, RY),
+ EXTRACT_CR(inst, CRD));
+}
+
+AVR32_INST_FORMAT(avr32_inst_reg_to_co) {
+ db_printf("cp%d, cr%d, %s",
+ EXTRACT_CP(inst),
+ EXTRACT_CR(inst, CRD),
+ EXTRACT_REG(inst, RY));
+}
+
+AVR32_INST_FORMAT(avr32_inst_co_load) {
+ db_printf("cp%d, cr%d, --%s",
+ EXTRACT_CP(inst),
+ EXTRACT_CR(inst, CRD),
+ EXTRACT_REG(inst, RY));
+}
+
+AVR32_INST_FORMAT(avr32_inst_co_store) {
+ db_printf("cp%d, %s++, cr%d",
+ EXTRACT_CP(inst),
+ EXTRACT_REG(inst, RY),
+ EXTRACT_CR(inst, CRD));
+}
+
+AVR32_INST_FORMAT(avr32_inst_co_disp_2shift_load) {
+ db_printf("cp%d, cr%d, %s[%s << %d]",
+ EXTRACT_CP(inst),
+ EXTRACT_CR(inst, CRD),
+ EXTRACT_REG(inst, RY),
+ EXTRACT_REG(inst, RD),
+ EXTRACT(inst, 0x00000030, 4));
+}
+
+AVR32_INST_FORMAT(avr32_inst_co_disp_2shift_store) {
+ db_printf("cp%d, %s[%s << %d], cr%d",
+ EXTRACT_CP(inst),
+ EXTRACT_REG(inst, RY),
+ EXTRACT_REG(inst, RD),
+ EXTRACT(inst, 0x00000030, 4),
+ EXTRACT_CR(inst, CRD));
+}
+
+AVR32_INST_FORMAT(avr32_inst_co_disp8_load) {
+ db_printf("cp%d, cr%d, %s[0x%x]",
+ EXTRACT_CP(inst),
+ EXTRACT_CR(inst, CRD),
+ EXTRACT_REG(inst, RY),
+ EXTRACT(inst, 0x000000FF, 0) << 2);
+
+}
+
+AVR32_INST_FORMAT(avr32_inst_co_disp8_store) {
+ db_printf("cp%d, %s[0x%x], cr%d",
+ EXTRACT_CP(inst),
+ EXTRACT_REG(inst, RY),
+ EXTRACT(inst, 0x000000FF, 0) << 2,
+ EXTRACT_CR(inst, CRD));
+}
+
+AVR32_INST_FORMAT(avr32_inst_co_load_many) {
+ char **list = (char **)arg;
+ int i, set;
+
+ db_printf("cp%d, %s%s, ",
+ EXTRACT_CP(inst),
+ EXTRACT_REG(inst, RY),
+ (inst & 0x00001000) ? "++" : "");
+
+ for (i = set = 0; i < 8; i++) {
+ if (inst & (1 << i)) {
+ if (set) {
+ db_printf(",");
+ }
+ db_printf("%s", list[i]);
+ set = 1;
+ }
+ }
+}
+
+AVR32_INST_FORMAT(avr32_inst_co_store_many) {
+ char **list = (char **)arg;
+ int i, set;
+
+ db_printf("cp%d, %s%s, ",
+ EXTRACT_CP(inst),
+ (inst & 0x00001000) ? "--" : "",
+ EXTRACT_REG(inst, RY));
+
+ for (i = set = 0; i < 8; i++) {
+ if (inst & (1 << i)) {
+ if (set) {
+ db_printf(",");
+ }
+ db_printf("%s", list[i]);
+ set = 1;
+ }
+ }
+}
+
+/*** Other */
+AVR32_INST_FORMAT(avr32_inst_sreg) {
+ db_printf("%d", EXTRACT(inst, 0x01F00000, 20));
+}
+
+AVR32_INST_FORMAT(avr32_inst_st_reg) {
+ db_printf("%s, 0x%x",
>>> TRUNCATED FOR MAIL (1000 lines) <<<
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