PERFORCE change 136521 for review

[Randall R. Stewart]

http://perforce.freebsd.org/chv.cgi?CH=136521

Change 136521 by rrs at rrs-mips2-jnpr on 2008/02/29 21:36:57

	Fixes strange UART reply of IIR_BUSY, if treated
	       like a read and write int it all works.
	       Also adds a ddb command to show oct_state (int reg
	       etc).

Affected files ...

.. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_dev_oct16550.c#12 edit

Differences ...

==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_dev_oct16550.c#12 (text+ko) ====

@@ -57,7 +57,7 @@
 
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD: src/sys/dev/uart/uart_dev_oct16550.c,v 1.23 2006/05/23 06:04:45 dev-id:0 Exp $");
-
+#include "opt_ddb.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
@@ -86,6 +86,8 @@
         bus_space_write_8((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
 #define uart_getreg(bas, reg)	\
 	bus_space_read_8((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
+
+
 /*
  * Clear pending interrupts. THRE is cleared by reading IIR. Data
  * that may have been received gets lost here.
@@ -535,6 +537,7 @@
 	return (sig);
 }
 
+
 static int
 oct16550_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
 {
@@ -622,7 +625,7 @@
 
 	bas = &sc->sc_bas;
 	uart_lock(sc->sc_hwmtx);
-
+	
 	iir = uart_getreg(bas, OCT_REG_IIR) & IIR_IMASK;
 	if (iir != IIR_NOPEND) {
 
@@ -648,7 +651,9 @@
 			ipend |= SER_INT_SIGCHG;
 
 		} else if (iir == IIR_BUSY) {
-			(void)uart_getreg(bas, OCT_REG_USR);
+		        ipend |= SER_INT_TXIDLE;
+			ipend |= SER_INT_RXREADY;
+			iir = uart_getreg(bas, OCT_REG_IIR) & IIR_IMASK;
 		}
 	}
 	uart_unlock(sc->sc_hwmtx);
@@ -812,12 +817,6 @@
 
 	bas = &sc->sc_bas;
 	uart_lock(sc->sc_hwmtx);
-#ifdef NO_UART_INTERRUPTS
-	for (i = 0; i < sc->sc_txdatasz; i++) {
-		oct16550_putc(bas, sc->sc_txbuf[i]);
-	}
-#else
-
 	oct16550_wait_txhr_empty(bas, 100, oct16550_delay(bas));
 	uart_setreg(bas, OCT_REG_IER, oct16550->ier | IER_ETXRDY);
 	uart_barrier(bas);
@@ -827,7 +826,64 @@
 		uart_barrier(bas);
 	}
 	sc->sc_txbusy = 1;
-#endif
 	uart_unlock(sc->sc_hwmtx);
 	return (0);
 }
+
+#ifdef DDB
+
+void db_dump_intr_state(void);
+
+void
+db_dump_intr_state(void)
+{
+	uint32_t status_bits;
+	uint64_t ciu_intr_reg_addr;
+	uint64_t regstate1, regstate2;
+	int i;
+	status_bits = mips_rd_status();
+	printf("Mips SR is currently %x\n", status_bits);
+
+	
+	printf("Core Interrupt summary's IP2/IP3\n");
+	ciu_intr_reg_addr = OCTEON_CIU_SUMMARY_BASE_ADDR;
+	for(i=0; i<16; i++) {
+	  regstate1 = oct_read64(ciu_intr_reg_addr);
+	  regstate2 = oct_read64(ciu_intr_reg_addr + 0x8);
+	  printf("Core:%d Reg:%llx IP2:%llx IP3:%llx\n",
+		 i, ciu_intr_reg_addr, regstate1, regstate2);
+	  /* next register set please */
+	  ciu_intr_reg_addr += 0x10;
+	}
+	printf("Core Interrupt enable 0 IP2/IP3\n");
+	ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR;
+	for(i=0; i<16; i++) {
+	  regstate1 = oct_read64(ciu_intr_reg_addr);
+	  regstate2 = oct_read64(ciu_intr_reg_addr + 0x10);
+	  printf("Core:%d Reg:%llx IP2:%llx IP3:%llx\n",
+		 i, ciu_intr_reg_addr, regstate1, regstate2);
+	  /* next register set please */
+	  ciu_intr_reg_addr += 0x10;
+	}
+	printf("Core Interrupt enable 1 IP2/IP3\n");
+	ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR + 0x8;
+	for(i=0; i<16; i++) {
+	  regstate1 = oct_read64(ciu_intr_reg_addr);
+	  regstate2 = oct_read64(ciu_intr_reg_addr + 0x10);
+	  printf("Core:%d Reg:%llx IP2:%llx IP3:%llx\n",
+		 i, ciu_intr_reg_addr, regstate1, regstate2);
+	  /* next register set please */
+	  ciu_intr_reg_addr += 0x10;
+	}
+
+}
+
+#include <sys/kernel.h>
+#include <ddb/ddb.h>
+
+DB_SHOW_COMMAND(oct_state, ddb_dump_intr_state)
+{
+  db_dump_intr_state();
+}
+
+#endif