PERFORCE change 154134 for review
Sam Leffler
sam at FreeBSD.org
Fri Dec 5 11:42:45 PST 2008
http://perforce.freebsd.org/chv.cgi?CH=154134
Change 154134 by sam at sam_ebb on 2008/12/05 19:41:50
fix indentation/style; gotta do some work in here so deal with
this so I don't go blind staring at the code
Affected files ...
.. //depot/projects/vap/sys/arm/xscale/ixp425/ixp425_npe.c#6 edit
Differences ...
==== //depot/projects/vap/sys/arm/xscale/ixp425/ixp425_npe.c#6 (text+ko) ====
@@ -103,23 +103,23 @@
#include <arm/xscale/ixp425/ixp425_npevar.h>
struct ixpnpe_softc {
- device_t sc_dev;
- bus_space_tag_t sc_iot;
- bus_space_handle_t sc_ioh;
- bus_size_t sc_size; /* size of mapped register window */
- struct resource *sc_irq; /* IRQ resource */
- void *sc_ih; /* interrupt handler */
- struct mtx sc_mtx; /* mailbox lock */
- uint32_t sc_msg[2]; /* reply msg collected in ixpnpe_intr */
- int sc_msgwaiting; /* sc_msg holds valid data */
+ device_t sc_dev;
+ bus_space_tag_t sc_iot;
+ bus_space_handle_t sc_ioh;
+ bus_size_t sc_size; /* size of mapped register window */
+ struct resource *sc_irq; /* IRQ resource */
+ void *sc_ih; /* interrupt handler */
+ struct mtx sc_mtx; /* mailbox lock */
+ uint32_t sc_msg[2]; /* reply msg collected in ixpnpe_intr */
+ int sc_msgwaiting; /* sc_msg holds valid data */
- int validImage; /* valid ucode image loaded */
- int started; /* NPE is started */
- uint8_t functionalityId;/* ucode functionality ID */
- int insMemSize; /* size of instruction memory */
- int dataMemSize; /* size of data memory */
- uint32_t savedExecCount;
- uint32_t savedEcsDbgCtxtReg2;
+ int validImage; /* valid ucode image loaded */
+ int started; /* NPE is started */
+ uint8_t functionalityId;/* ucode functionality ID */
+ int insMemSize; /* size of instruction memory */
+ int dataMemSize; /* size of data memory */
+ uint32_t savedExecCount;
+ uint32_t savedEcsDbgCtxtReg2;
};
#define IX_NPEDL_NPEIMAGE_FIELD_MASK 0xff
@@ -144,37 +144,37 @@
#define IX_NPEDL_STATE_INFO_ENTRY_SIZE 2
typedef struct {
- uint32_t type;
- uint32_t offset;
+ uint32_t type;
+ uint32_t offset;
} IxNpeDlNpeMgrDownloadMapBlockEntry;
typedef union {
- IxNpeDlNpeMgrDownloadMapBlockEntry block;
- uint32_t eodmMarker;
+ IxNpeDlNpeMgrDownloadMapBlockEntry block;
+ uint32_t eodmMarker;
} IxNpeDlNpeMgrDownloadMapEntry;
typedef struct {
- /* 1st entry in the download map (there may be more than one) */
- IxNpeDlNpeMgrDownloadMapEntry entry[1];
+ /* 1st entry in the download map (there may be more than one) */
+ IxNpeDlNpeMgrDownloadMapEntry entry[1];
} IxNpeDlNpeMgrDownloadMap;
/* used to access an instruction or data block in a microcode image */
typedef struct {
- uint32_t npeMemAddress;
- uint32_t size;
- uint32_t data[1];
+ uint32_t npeMemAddress;
+ uint32_t size;
+ uint32_t data[1];
} IxNpeDlNpeMgrCodeBlock;
/* used to access each Context Reg entry state-information block */
typedef struct {
- uint32_t addressInfo;
- uint32_t value;
+ uint32_t addressInfo;
+ uint32_t value;
} IxNpeDlNpeMgrStateInfoCtxtRegEntry;
/* used to access a state-information block in a microcode image */
typedef struct {
- uint32_t size;
- IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1];
+ uint32_t size;
+ IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1];
} IxNpeDlNpeMgrStateInfoBlock;
static int npe_debug = 0;
@@ -233,137 +233,140 @@
static uint32_t
npe_reg_read(struct ixpnpe_softc *sc, bus_size_t off)
{
- uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, off);
- DPRINTFn(9, sc->sc_dev, "%s(0x%lx) => 0x%x\n", __func__, off, v);
- return v;
+ uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, off);
+ DPRINTFn(9, sc->sc_dev, "%s(0x%lx) => 0x%x\n", __func__, off, v);
+ return v;
}
static void
npe_reg_write(struct ixpnpe_softc *sc, bus_size_t off, uint32_t val)
{
- DPRINTFn(9, sc->sc_dev, "%s(0x%lx, 0x%x)\n", __func__, off, val);
- bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
+ DPRINTFn(9, sc->sc_dev, "%s(0x%lx, 0x%x)\n", __func__, off, val);
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
}
struct ixpnpe_softc *
ixpnpe_attach(device_t dev, int npeid)
{
- struct npeconfig {
- uint32_t base;
- uint32_t size;
- int irq;
- uint32_t ins_memsize;
- uint32_t data_memsize;
- };
- static const struct npeconfig npeconfigs[NPE_MAX] = {
- [NPE_A] = {
- .base = IXP425_NPE_A_HWBASE,
- .size = IXP425_NPE_A_SIZE,
- .irq = IXP425_INT_NPE_A,
- .ins_memsize = IX_NPEDL_INS_MEMSIZE_WORDS_NPEA,
- .data_memsize = IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
- },
- [NPE_B] = {
- .base = IXP425_NPE_B_HWBASE,
- .size = IXP425_NPE_B_SIZE,
- .irq = IXP425_INT_NPE_B,
- .ins_memsize = IX_NPEDL_INS_MEMSIZE_WORDS_NPEB,
- .data_memsize = IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
- },
- [NPE_C] = {
- .base = IXP425_NPE_C_HWBASE,
- .size = IXP425_NPE_C_SIZE,
- .irq = IXP425_INT_NPE_C,
- .ins_memsize = IX_NPEDL_INS_MEMSIZE_WORDS_NPEC,
- .data_memsize = IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
- },
- };
- struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
- struct ixpnpe_softc *sc;
- const struct npeconfig *config;
- int rid;
+ struct npeconfig {
+ uint32_t base;
+ uint32_t size;
+ int irq;
+ uint32_t ins_memsize;
+ uint32_t data_memsize;
+ };
+ static const struct npeconfig npeconfigs[NPE_MAX] = {
+ [NPE_A] = {
+ .base = IXP425_NPE_A_HWBASE,
+ .size = IXP425_NPE_A_SIZE,
+ .irq = IXP425_INT_NPE_A,
+ .ins_memsize = IX_NPEDL_INS_MEMSIZE_WORDS_NPEA,
+ .data_memsize = IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
+ },
+ [NPE_B] = {
+ .base = IXP425_NPE_B_HWBASE,
+ .size = IXP425_NPE_B_SIZE,
+ .irq = IXP425_INT_NPE_B,
+ .ins_memsize = IX_NPEDL_INS_MEMSIZE_WORDS_NPEB,
+ .data_memsize = IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
+ },
+ [NPE_C] = {
+ .base = IXP425_NPE_C_HWBASE,
+ .size = IXP425_NPE_C_SIZE,
+ .irq = IXP425_INT_NPE_C,
+ .ins_memsize = IX_NPEDL_INS_MEMSIZE_WORDS_NPEC,
+ .data_memsize = IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
+ },
+ };
+ struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
+ struct ixpnpe_softc *sc;
+ const struct npeconfig *config;
+ int rid;
- if (npeid >= NPE_MAX) {
- device_printf(dev, "bad npeid %d passed to %s\n", npeid, __func__);
- return NULL;
- }
- config = &npeconfigs[npeid];
+ if (npeid >= NPE_MAX) {
+ device_printf(dev, "%s: bad npeid %d\n", __func__, npeid);
+ return NULL;
+ }
+ config = &npeconfigs[npeid];
- /* XXX M_BUS */
- sc = malloc(sizeof(struct ixpnpe_softc), M_TEMP, M_WAITOK | M_ZERO);
- sc->sc_dev = dev;
- sc->sc_iot = sa->sc_iot;
- mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "npe driver", MTX_DEF);
+ /* XXX M_BUS */
+ sc = malloc(sizeof(struct ixpnpe_softc), M_TEMP, M_WAITOK | M_ZERO);
+ sc->sc_dev = dev;
+ sc->sc_iot = sa->sc_iot;
+ mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "npe driver", MTX_DEF);
- sc->sc_size = config->size;
- sc->insMemSize = config->ins_memsize; /* size of instruction memory */
- sc->dataMemSize = config->data_memsize; /* size of data memory */
+ sc->sc_size = config->size;
+ sc->insMemSize = config->ins_memsize; /* size of instruction memory */
+ sc->dataMemSize = config->data_memsize; /* size of data memory */
- if (bus_space_map(sc->sc_iot, config->base, sc->sc_size, 0, &sc->sc_ioh))
- panic("%s: Cannot map registers", device_get_name(dev));
+ if (bus_space_map(sc->sc_iot, config->base, sc->sc_size, 0, &sc->sc_ioh))
+ panic("%s: Cannot map registers", device_get_name(dev));
- /*
- * Setup IRQ and handler for NPE message support.
- */
- rid = 0;
- sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
- config->irq, config->irq, 1, RF_ACTIVE);
- if (!sc->sc_irq)
- panic("%s: Unable to allocate irq %u", device_get_name(dev), config->irq);
- /* XXX could be a source of entropy */
- bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
- NULL, ixpnpe_intr, sc, &sc->sc_ih);
- /* enable output fifo interrupts (NB: must also set OFIFO Write Enable) */
- npe_reg_write(sc, IX_NPECTL,
- npe_reg_read(sc, IX_NPECTL) | (IX_NPECTL_OFE | IX_NPECTL_OFWE));
+ /*
+ * Setup IRQ and handler for NPE message support.
+ */
+ rid = 0;
+ sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
+ config->irq, config->irq, 1, RF_ACTIVE);
+ if (sc->sc_irq == NULL)
+ panic("%s: Unable to allocate irq %u", device_get_name(dev),
+ config->irq);
+ /* XXX could be a source of entropy */
+ bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
+ NULL, ixpnpe_intr, sc, &sc->sc_ih);
+ /*
+ * Enable output fifo interrupts (NB: must also set OFIFO Write Enable)
+ */
+ npe_reg_write(sc, IX_NPECTL,
+ npe_reg_read(sc, IX_NPECTL) | (IX_NPECTL_OFE | IX_NPECTL_OFWE));
- return sc;
+ return sc;
}
void
ixpnpe_detach(struct ixpnpe_softc *sc)
{
- /* disable output fifo interrupts */
- npe_reg_write(sc, IX_NPECTL,
- npe_reg_read(sc, IX_NPECTL) &~ (IX_NPECTL_OFE | IX_NPECTL_OFWE));
+ /* disable output fifo interrupts */
+ npe_reg_write(sc, IX_NPECTL,
+ npe_reg_read(sc, IX_NPECTL) &~ (IX_NPECTL_OFE | IX_NPECTL_OFWE));
- bus_teardown_intr(sc->sc_dev, sc->sc_irq, sc->sc_ih);
- bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size);
- mtx_destroy(&sc->sc_mtx);
- free(sc, M_TEMP);
+ bus_teardown_intr(sc->sc_dev, sc->sc_irq, sc->sc_ih);
+ bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size);
+ mtx_destroy(&sc->sc_mtx);
+ free(sc, M_TEMP);
}
int
ixpnpe_stopandreset(struct ixpnpe_softc *sc)
{
- int error;
+ int error;
- mtx_lock(&sc->sc_mtx);
- error = npe_cpu_stop(sc); /* stop NPE */
- if (error == 0)
- error = npe_cpu_reset(sc); /* reset it */
- if (error == 0)
- sc->started = 0; /* mark stopped */
- mtx_unlock(&sc->sc_mtx);
+ mtx_lock(&sc->sc_mtx);
+ error = npe_cpu_stop(sc); /* stop NPE */
+ if (error == 0)
+ error = npe_cpu_reset(sc); /* reset it */
+ if (error == 0)
+ sc->started = 0; /* mark stopped */
+ mtx_unlock(&sc->sc_mtx);
- DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error);
- return error;
+ DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error);
+ return error;
}
static int
ixpnpe_start_locked(struct ixpnpe_softc *sc)
{
- int error;
+ int error;
- if (!sc->started) {
- error = npe_cpu_start(sc);
- if (error == 0)
- sc->started = 1;
- } else
- error = 0;
+ if (!sc->started) {
+ error = npe_cpu_start(sc);
+ if (error == 0)
+ sc->started = 1;
+ } else
+ error = 0;
- DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error);
- return error;
+ DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error);
+ return error;
}
int
@@ -380,16 +383,16 @@
int
ixpnpe_stop(struct ixpnpe_softc *sc)
{
- int error;
+ int error;
- mtx_lock(&sc->sc_mtx);
- error = npe_cpu_stop(sc);
- if (error == 0)
- sc->started = 0;
- mtx_unlock(&sc->sc_mtx);
+ mtx_lock(&sc->sc_mtx);
+ error = npe_cpu_stop(sc);
+ if (error == 0)
+ sc->started = 0;
+ mtx_unlock(&sc->sc_mtx);
- DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error);
- return error;
+ DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error);
+ return error;
}
/*
@@ -402,9 +405,9 @@
* NPE Image Header definition, used in new NPE Image Library format
*/
typedef struct {
- uint32_t marker;
- uint32_t id;
- uint32_t size;
+ uint32_t marker;
+ uint32_t id;
+ uint32_t size;
} IxNpeDlImageMgrImageHeader;
static int
@@ -412,210 +415,219 @@
const uint32_t *imageLibrary, uint32_t imageId,
const uint32_t **imagePtr, uint32_t *imageSize)
{
- const IxNpeDlImageMgrImageHeader *image;
- uint32_t offset = 0;
+ const IxNpeDlImageMgrImageHeader *image;
+ uint32_t offset = 0;
- while (imageLibrary[offset] == NPE_IMAGE_MARKER) {
- image = (const IxNpeDlImageMgrImageHeader *)&imageLibrary[offset];
- offset += sizeof(IxNpeDlImageMgrImageHeader)/sizeof(uint32_t);
-
- DPRINTF(sc->sc_dev, "%s: off %u mark 0x%x id 0x%x size %u\n",
- __func__, offset, image->marker, image->id, image->size);
- if (image->id == imageId) {
- *imagePtr = imageLibrary + offset;
- *imageSize = image->size;
- return 0;
- }
- /* 2 consecutive NPE_IMAGE_MARKER's indicates end of library */
- if (image->id == NPE_IMAGE_MARKER) {
- DPRINTF(sc->sc_dev,
- "imageId 0x%08x not found in image library header\n", imageId);
- /* reached end of library, image not found */
- return ESRCH;
- }
- offset += image->size;
- }
- return ESRCH;
+ while (imageLibrary[offset] == NPE_IMAGE_MARKER) {
+ image = (const IxNpeDlImageMgrImageHeader *)
+ &imageLibrary[offset];
+ offset += sizeof(IxNpeDlImageMgrImageHeader)/sizeof(uint32_t);
+
+ DPRINTF(sc->sc_dev, "%s: off %u mark 0x%x id 0x%x size %u\n",
+ __func__, offset, image->marker, image->id, image->size);
+ if (image->id == imageId) {
+ *imagePtr = imageLibrary + offset;
+ *imageSize = image->size;
+ return 0;
+ }
+ /* 2 consecutive NPE_IMAGE_MARKER's indicates end of library */
+ if (image->id == NPE_IMAGE_MARKER) {
+ DPRINTF(sc->sc_dev,
+ "imageId 0x%08x not found in image library header\n",
+ imageId);
+ /* reached end of library, image not found */
+ return ESRCH;
+ }
+ offset += image->size;
+ }
+ return ESRCH;
}
int
ixpnpe_init(struct ixpnpe_softc *sc, const char *imageName, uint32_t imageId)
{
- static const char *devname[4] =
- { "IXP425", "IXP465", "DeviceID#2", "DeviceID#3" };
- uint32_t imageSize;
- const uint32_t *imageCodePtr;
- const struct firmware *fw;
- int error;
+ static const char *devname[4] =
+ { "IXP425", "IXP465", "DeviceID#2", "DeviceID#3" };
+ uint32_t imageSize;
+ const uint32_t *imageCodePtr;
+ const struct firmware *fw;
+ int error;
- DPRINTF(sc->sc_dev, "load %s, imageId 0x%08x\n", imageName, imageId);
+ DPRINTF(sc->sc_dev, "load %s, imageId 0x%08x\n", imageName, imageId);
#if 0
- IxFeatureCtrlDeviceId devid = IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId);
- /*
- * Checking if image being loaded is meant for device that is running.
- * Image is forward compatible. i.e Image built for IXP42X should run
- * on IXP46X but not vice versa.
- */
- if (devid > (ixFeatureCtrlDeviceRead() & IX_FEATURE_CTRL_DEVICE_TYPE_MASK))
- return EINVAL;
+ IxFeatureCtrlDeviceId devid = IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId);
+ /*
+ * Checking if image being loaded is meant for device that is running.
+ * Image is forward compatible. i.e Image built for IXP42X should run
+ * on IXP46X but not vice versa.
+ */
+ if (devid > (ixFeatureCtrlDeviceRead() & IX_FEATURE_CTRL_DEVICE_TYPE_MASK))
+ return EINVAL;
#endif
- error = ixpnpe_stopandreset(sc); /* stop and reset the NPE */
- if (error != 0)
- return error;
+ error = ixpnpe_stopandreset(sc); /* stop and reset the NPE */
+ if (error != 0)
+ return error;
- fw = firmware_get(imageName);
- if (fw == NULL)
- return ENOENT;
+ fw = firmware_get(imageName);
+ if (fw == NULL)
+ return ENOENT;
- /* Locate desired image in files w/ combined images */
- error = npe_findimage(sc, fw->data, imageId, &imageCodePtr, &imageSize);
- if (error != 0)
- goto done;
+ /* Locate desired image in files w/ combined images */
+ error = npe_findimage(sc, fw->data, imageId, &imageCodePtr, &imageSize);
+ if (error != 0)
+ goto done;
- device_printf(sc->sc_dev,
- "load fw image %s.NPE-%c Func 0x%x Rev %u.%u\n",
- devname[NPEIMAGE_DEVID(imageId)], 'A' + NPEIMAGE_NPEID(imageId),
- NPEIMAGE_FUNCID(imageId), NPEIMAGE_MAJOR(imageId),
- NPEIMAGE_MINOR(imageId));
+ device_printf(sc->sc_dev,
+ "load fw image %s.NPE-%c Func 0x%x Rev %u.%u\n",
+ devname[NPEIMAGE_DEVID(imageId)], 'A' + NPEIMAGE_NPEID(imageId),
+ NPEIMAGE_FUNCID(imageId), NPEIMAGE_MAJOR(imageId),
+ NPEIMAGE_MINOR(imageId));
- /*
- * If download was successful, store image Id in list of
- * currently loaded images. If a critical error occured
- * during download, record that the NPE has an invalid image
- */
- mtx_lock(&sc->sc_mtx);
- error = npe_load_image(sc, imageCodePtr, 1 /*VERIFY*/);
- if (error == 0) {
- sc->validImage = 1;
- error = ixpnpe_start_locked(sc);
- } else {
- sc->validImage = 0;
- }
- sc->functionalityId = IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId);
- mtx_unlock(&sc->sc_mtx);
+ /*
+ * If download was successful, store image Id in list of
+ * currently loaded images. If a critical error occured
+ * during download, record that the NPE has an invalid image
+ */
+ mtx_lock(&sc->sc_mtx);
+ error = npe_load_image(sc, imageCodePtr, 1 /*VERIFY*/);
+ if (error == 0) {
+ sc->validImage = 1;
+ error = ixpnpe_start_locked(sc);
+ } else {
+ sc->validImage = 0;
+ }
+ sc->functionalityId = IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId);
+ mtx_unlock(&sc->sc_mtx);
done:
- firmware_put(fw, FIRMWARE_UNLOAD);
- DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error);
- return error;
+ firmware_put(fw, FIRMWARE_UNLOAD);
+ DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error);
+ return error;
}
int
ixpnpe_getfunctionality(struct ixpnpe_softc *sc)
{
- return (sc->validImage ? sc->functionalityId : 0);
+ return (sc->validImage ? sc->functionalityId : 0);
}
static int
npe_checkbits(struct ixpnpe_softc *sc, uint32_t reg, uint32_t expectedBitsSet)
{
- uint32_t val;
+ uint32_t val;
- val = npe_reg_read(sc, reg);
- DPRINTFn(5, sc->sc_dev, "%s(0x%x, 0x%x) => 0x%x (%u)\n",
- __func__, reg, expectedBitsSet, val,
- (val & expectedBitsSet) == expectedBitsSet);
- return ((val & expectedBitsSet) == expectedBitsSet);
+ val = npe_reg_read(sc, reg);
+ DPRINTFn(5, sc->sc_dev, "%s(0x%x, 0x%x) => 0x%x (%u)\n",
+ __func__, reg, expectedBitsSet, val,
+ (val & expectedBitsSet) == expectedBitsSet);
+ return ((val & expectedBitsSet) == expectedBitsSet);
}
static int
npe_isstopped(struct ixpnpe_softc *sc)
{
- return npe_checkbits(sc,
- IX_NPEDL_REG_OFFSET_EXCTL, IX_NPEDL_EXCTL_STATUS_STOP);
+ return npe_checkbits(sc,
+ IX_NPEDL_REG_OFFSET_EXCTL, IX_NPEDL_EXCTL_STATUS_STOP);
}
static int
npe_load_ins(struct ixpnpe_softc *sc,
const IxNpeDlNpeMgrCodeBlock *bp, int verify)
{
- uint32_t npeMemAddress;
- int i, blockSize;
+ uint32_t npeMemAddress;
+ int i, blockSize;
- npeMemAddress = bp->npeMemAddress;
- blockSize = bp->size; /* NB: instruction/data count */
- if (npeMemAddress + blockSize > sc->insMemSize) {
- device_printf(sc->sc_dev, "Block size too big for NPE memory\n");
- return EINVAL; /* XXX */
- }
- for (i = 0; i < blockSize; i++, npeMemAddress++) {
- if (npe_ins_write(sc, npeMemAddress, bp->data[i], verify) != 0) {
- device_printf(sc->sc_dev, "NPE instruction write failed");
- return EIO;
+ npeMemAddress = bp->npeMemAddress;
+ blockSize = bp->size; /* NB: instruction/data count */
+ if (npeMemAddress + blockSize > sc->insMemSize) {
+ device_printf(sc->sc_dev,
+ "Block size %u too big for NPE memory\n", blockSize);
+ return EINVAL; /* XXX */
+ }
+ for (i = 0; i < blockSize; i++, npeMemAddress++) {
+ if (npe_ins_write(sc, npeMemAddress, bp->data[i], verify) != 0) {
+ device_printf(sc->sc_dev,
+ "NPE instruction write failed");
+ return EIO;
+ }
}
- }
- return 0;
+ return 0;
}
static int
npe_load_data(struct ixpnpe_softc *sc,
const IxNpeDlNpeMgrCodeBlock *bp, int verify)
{
- uint32_t npeMemAddress;
- int i, blockSize;
+ uint32_t npeMemAddress;
+ int i, blockSize;
- npeMemAddress = bp->npeMemAddress;
- blockSize = bp->size; /* NB: instruction/data count */
- if (npeMemAddress + blockSize > sc->dataMemSize) {
- device_printf(sc->sc_dev, "Block size too big for NPE memory\n");
- return EINVAL;
- }
- for (i = 0; i < blockSize; i++, npeMemAddress++) {
- if (npe_data_write(sc, npeMemAddress, bp->data[i], verify) != 0) {
- device_printf(sc->sc_dev, "NPE data write failed\n");
- return EIO;
+ npeMemAddress = bp->npeMemAddress;
+ blockSize = bp->size; /* NB: instruction/data count */
+ if (npeMemAddress + blockSize > sc->dataMemSize) {
+ device_printf(sc->sc_dev,
+ "Block size %u too big for NPE memory\n", blockSize);
+ return EINVAL;
+ }
+ for (i = 0; i < blockSize; i++, npeMemAddress++) {
+ if (npe_data_write(sc, npeMemAddress, bp->data[i], verify) != 0) {
+ device_printf(sc->sc_dev, "NPE data write failed\n");
+ return EIO;
+ }
}
- }
- return 0;
+ return 0;
}
static int
npe_load_stateinfo(struct ixpnpe_softc *sc,
const IxNpeDlNpeMgrStateInfoBlock *bp, int verify)
{
- int i, nentries, error;
-
- npe_cpu_step_save(sc);
+ int i, nentries, error;
+
+ npe_cpu_step_save(sc);
- /* for each state-info context register entry in block */
- nentries = bp->size / IX_NPEDL_STATE_INFO_ENTRY_SIZE;
- error = 0;
- for (i = 0; i < nentries; i++) {
- /* each state-info entry is 2 words (address, value) in length */
- uint32_t regVal = bp->ctxtRegEntry[i].value;
- uint32_t addrInfo = bp->ctxtRegEntry[i].addressInfo;
+ /* for each state-info context register entry in block */
+ nentries = bp->size / IX_NPEDL_STATE_INFO_ENTRY_SIZE;
+ error = 0;
+ for (i = 0; i < nentries; i++) {
+ /* each state-info entry is 2 words (address, value) */
+ uint32_t regVal = bp->ctxtRegEntry[i].value;
+ uint32_t addrInfo = bp->ctxtRegEntry[i].addressInfo;
- uint32_t reg = (addrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG);
- uint32_t cNum = (addrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >>
- IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM;
-
- /* error-check Context Register No. and Context Number values */
- if (!(0 <= reg && reg < IX_NPEDL_CTXT_REG_MAX)) {
- device_printf(sc->sc_dev, "invalid Context Register %u\n", reg);
- error = EINVAL;
- break;
- }
- if (!(0 <= cNum && cNum < IX_NPEDL_CTXT_NUM_MAX)) {
- device_printf(sc->sc_dev, "invalid Context Number %u\n", cNum);
- error = EINVAL;
- break;
- }
- /* NOTE that there is no STEVT register for Context 0 */
- if (cNum == 0 && reg == IX_NPEDL_CTXT_REG_STEVT) {
- device_printf(sc->sc_dev, "no STEVT for Context 0\n");
- error = EINVAL;
- break;
- }
+ uint32_t reg = (addrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG);
+ uint32_t cNum = (addrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >>
+ IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM;
+
+ /* error-check Context Register No. and Context Number values */
+ if (!(0 <= reg && reg < IX_NPEDL_CTXT_REG_MAX)) {
+ device_printf(sc->sc_dev,
+ "invalid Context Register %u\n", reg);
+ error = EINVAL;
+ break;
+ }
+ if (!(0 <= cNum && cNum < IX_NPEDL_CTXT_NUM_MAX)) {
+ device_printf(sc->sc_dev,
+ "invalid Context Number %u\n", cNum);
+ error = EINVAL;
+ break;
+ }
+ /* NOTE that there is no STEVT register for Context 0 */
+ if (cNum == 0 && reg == IX_NPEDL_CTXT_REG_STEVT) {
+ device_printf(sc->sc_dev,
+ "no STEVT for Context 0\n");
+ error = EINVAL;
+ break;
+ }
- if (npe_ctx_reg_write(sc, cNum, reg, regVal, verify) != 0) {
- device_printf(sc->sc_dev, "write of state-info to NPE failed\n");
- error = EIO;
- break;
+ if (npe_ctx_reg_write(sc, cNum, reg, regVal, verify) != 0) {
+ device_printf(sc->sc_dev,
+ "write of state-info to NPE failed\n");
+ error = EIO;
+ break;
+ }
}
- }
- npe_cpu_step_restore(sc);
- return error;
+ npe_cpu_step_restore(sc);
+ return error;
}
static int
@@ -623,79 +635,84 @@
const uint32_t *imageCodePtr, int verify)
{
#define EOM(marker) ((marker) == IX_NPEDL_END_OF_DOWNLOAD_MAP)
- const IxNpeDlNpeMgrDownloadMap *downloadMap;
- int i, error;
+ const IxNpeDlNpeMgrDownloadMap *downloadMap;
+ int i, error;
- if (!npe_isstopped(sc)) { /* verify NPE is stopped */
- device_printf(sc->sc_dev, "cannot load image, NPE not stopped\n");
- return EIO;
- }
+ if (!npe_isstopped(sc)) { /* verify NPE is stopped */
+ device_printf(sc->sc_dev,
+ "cannot load image, NPE not stopped\n");
+ return EIO;
+ }
- /*
- * Read Download Map, checking each block type and calling
- * appropriate function to perform download
- */
- error = 0;
- downloadMap = (const IxNpeDlNpeMgrDownloadMap *) imageCodePtr;
- for (i = 0; !EOM(downloadMap->entry[i].eodmMarker); i++) {
- /* calculate pointer to block to be downloaded */
- const uint32_t *bp = imageCodePtr + downloadMap->entry[i].block.offset;
- switch (downloadMap->entry[i].block.type) {
- case IX_NPEDL_BLOCK_TYPE_INSTRUCTION:
- error = npe_load_ins(sc,
- (const IxNpeDlNpeMgrCodeBlock *) bp, verify);
- DPRINTF(sc->sc_dev, "%s: inst, error %d\n", __func__, error);
- break;
- case IX_NPEDL_BLOCK_TYPE_DATA:
- error = npe_load_data(sc,
- (const IxNpeDlNpeMgrCodeBlock *) bp, verify);
- DPRINTF(sc->sc_dev, "%s: data, error %d\n", __func__, error);
- break;
- case IX_NPEDL_BLOCK_TYPE_STATE:
- error = npe_load_stateinfo(sc,
- (const IxNpeDlNpeMgrStateInfoBlock *) bp, verify);
- DPRINTF(sc->sc_dev, "%s: state, error %d\n", __func__, error);
- break;
- default:
- device_printf(sc->sc_dev,
- "unknown block type 0x%x in download map\n",
- downloadMap->entry[i].block.type);
- error = EIO; /* XXX */
- break;
+ /*
+ * Read Download Map, checking each block type and calling
+ * appropriate function to perform download
+ */
+ error = 0;
+ downloadMap = (const IxNpeDlNpeMgrDownloadMap *) imageCodePtr;
+ for (i = 0; !EOM(downloadMap->entry[i].eodmMarker); i++) {
+ /* calculate pointer to block to be downloaded */
+ const uint32_t *bp = imageCodePtr +
+ downloadMap->entry[i].block.offset;
+ switch (downloadMap->entry[i].block.type) {
+ case IX_NPEDL_BLOCK_TYPE_INSTRUCTION:
+ error = npe_load_ins(sc,
+ (const IxNpeDlNpeMgrCodeBlock *) bp, verify);
+ DPRINTF(sc->sc_dev, "%s: inst, error %d\n",
+ __func__, error);
+ break;
+ case IX_NPEDL_BLOCK_TYPE_DATA:
+ error = npe_load_data(sc,
+ (const IxNpeDlNpeMgrCodeBlock *) bp, verify);
+ DPRINTF(sc->sc_dev, "%s: data, error %d\n",
+ __func__, error);
+ break;
+ case IX_NPEDL_BLOCK_TYPE_STATE:
+ error = npe_load_stateinfo(sc,
+ (const IxNpeDlNpeMgrStateInfoBlock *) bp, verify);
+ DPRINTF(sc->sc_dev, "%s: state, error %d\n",
+ __func__, error);
+ break;
+ default:
+ device_printf(sc->sc_dev,
+ "unknown block type 0x%x in download map\n",
+ downloadMap->entry[i].block.type);
+ error = EIO; /* XXX */
+ break;
+ }
+ if (error != 0)
+ break;
}
- if (error != 0)
- break;
- }
- return error;
+ return error;
#undef EOM
}
/* contains Reset values for Context Store Registers */
static const struct {
- uint32_t regAddr;
- uint32_t regResetVal;
+ uint32_t regAddr;
+ uint32_t regResetVal;
} ixNpeDlEcsRegResetValues[] = {
- { IX_NPEDL_ECS_BG_CTXT_REG_0, IX_NPEDL_ECS_BG_CTXT_REG_0_RESET },
- { IX_NPEDL_ECS_BG_CTXT_REG_1, IX_NPEDL_ECS_BG_CTXT_REG_1_RESET },
- { IX_NPEDL_ECS_BG_CTXT_REG_2, IX_NPEDL_ECS_BG_CTXT_REG_2_RESET },
- { IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET },
- { IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET },
- { IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET },
- { IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET },
- { IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET },
- { IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET },
- { IX_NPEDL_ECS_DBG_CTXT_REG_0, IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET },
- { IX_NPEDL_ECS_DBG_CTXT_REG_1, IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET },
- { IX_NPEDL_ECS_DBG_CTXT_REG_2, IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET },
- { IX_NPEDL_ECS_INSTRUCT_REG, IX_NPEDL_ECS_INSTRUCT_REG_RESET }
+ { IX_NPEDL_ECS_BG_CTXT_REG_0, IX_NPEDL_ECS_BG_CTXT_REG_0_RESET },
+ { IX_NPEDL_ECS_BG_CTXT_REG_1, IX_NPEDL_ECS_BG_CTXT_REG_1_RESET },
+ { IX_NPEDL_ECS_BG_CTXT_REG_2, IX_NPEDL_ECS_BG_CTXT_REG_2_RESET },
+ { IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET },
+ { IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET },
+ { IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET },
+ { IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET },
+ { IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET },
+ { IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET },
+ { IX_NPEDL_ECS_DBG_CTXT_REG_0, IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET },
+ { IX_NPEDL_ECS_DBG_CTXT_REG_1, IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET },
+ { IX_NPEDL_ECS_DBG_CTXT_REG_2, IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET },
+ { IX_NPEDL_ECS_INSTRUCT_REG, IX_NPEDL_ECS_INSTRUCT_REG_RESET }
};
/* contains Reset values for Context Store Registers */
static const uint32_t ixNpeDlCtxtRegResetValues[] = {
- IX_NPEDL_CTXT_REG_RESET_STEVT,
- IX_NPEDL_CTXT_REG_RESET_STARTPC,
- IX_NPEDL_CTXT_REG_RESET_REGMAP,
- IX_NPEDL_CTXT_REG_RESET_CINDEX,
+ IX_NPEDL_CTXT_REG_RESET_STEVT,
+ IX_NPEDL_CTXT_REG_RESET_STARTPC,
+ IX_NPEDL_CTXT_REG_RESET_REGMAP,
+ IX_NPEDL_CTXT_REG_RESET_CINDEX,
};
#define IX_NPEDL_RESET_NPE_PARITY 0x0800
@@ -706,212 +723,217 @@
npe_cpu_reset(struct ixpnpe_softc *sc)
{
#define N(a) (sizeof(a) / sizeof(a[0]))
- struct ixp425_softc *sa = device_get_softc(device_get_parent(sc->sc_dev));
- uint32_t ctxtReg; /* identifies Context Store reg (0-3) */
- uint32_t regAddr;
- uint32_t regVal;
- uint32_t resetNpeParity;
- uint32_t ixNpeConfigCtrlRegVal;
- int i, error = 0;
-
- /* pre-store the NPE Config Control Register Value */
- ixNpeConfigCtrlRegVal = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_CTL);
- ixNpeConfigCtrlRegVal |= 0x3F000000;
+ struct ixp425_softc *sa =
+ device_get_softc(device_get_parent(sc->sc_dev));
+ uint32_t ctxtReg; /* identifies Context Store reg (0-3) */
+ uint32_t regAddr;
+ uint32_t regVal;
+ uint32_t resetNpeParity;
+ uint32_t ixNpeConfigCtrlRegVal;
+ int i, error = 0;
+
+ /* pre-store the NPE Config Control Register Value */
+ ixNpeConfigCtrlRegVal = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_CTL);
+ ixNpeConfigCtrlRegVal |= 0x3F000000;
- /* disable the parity interrupt */
- npe_reg_write(sc, IX_NPEDL_REG_OFFSET_CTL,
- (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK));
- DPRINTFn(2, sc->sc_dev, "%s: dis parity int, CTL => 0x%x\n",
- __func__, ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK);
-
- npe_cpu_step_save(sc);
+ /* disable the parity interrupt */
+ npe_reg_write(sc, IX_NPEDL_REG_OFFSET_CTL,
+ (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK));
+ DPRINTFn(2, sc->sc_dev, "%s: dis parity int, CTL => 0x%x\n",
+ __func__, ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK);
+
+ npe_cpu_step_save(sc);
- /*
- * Clear the FIFOs.
- */
- while (npe_checkbits(sc,
- IX_NPEDL_REG_OFFSET_WFIFO, IX_NPEDL_MASK_WFIFO_VALID)) {
- /* read from the Watch-point FIFO until empty */
- (void) npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WFIFO);
- }
+ /*
+ * Clear the FIFOs.
+ */
+ while (npe_checkbits(sc,
+ IX_NPEDL_REG_OFFSET_WFIFO, IX_NPEDL_MASK_WFIFO_VALID)) {
+ /* read from the Watch-point FIFO until empty */
+ (void) npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WFIFO);
+ }
- while (npe_checkbits(sc,
- IX_NPEDL_REG_OFFSET_STAT, IX_NPEDL_MASK_STAT_OFNE)) {
- /* read from the outFIFO until empty */
- (void) npe_reg_read(sc, IX_NPEDL_REG_OFFSET_FIFO);
- }
-
- while (npe_checkbits(sc,
- IX_NPEDL_REG_OFFSET_STAT, IX_NPEDL_MASK_STAT_IFNE)) {
+ while (npe_checkbits(sc,
+ IX_NPEDL_REG_OFFSET_STAT, IX_NPEDL_MASK_STAT_OFNE)) {
+ /* read from the outFIFO until empty */
+ (void) npe_reg_read(sc, IX_NPEDL_REG_OFFSET_FIFO);
+ }
+
+ while (npe_checkbits(sc,
+ IX_NPEDL_REG_OFFSET_STAT, IX_NPEDL_MASK_STAT_IFNE)) {
+ /*
+ * Step execution of the NPE intruction to read inFIFO using
+ * the Debug Executing Context stack.
+ */
+ error = npe_cpu_step(sc, IX_NPEDL_INSTR_RD_FIFO, 0, 0);
+ if (error != 0) {
+ DPRINTF(sc->sc_dev, "%s: cannot step (1), error %u\n",
+ __func__, error);
+ npe_cpu_step_restore(sc);
+ return error;
+ }
+ }
+
/*
- * Step execution of the NPE intruction to read inFIFO using
- * the Debug Executing Context stack.
+ * Reset the mailbox reg
*/
- error = npe_cpu_step(sc, IX_NPEDL_INSTR_RD_FIFO, 0, 0);
+ /* ...from XScale side */
+ npe_reg_write(sc, IX_NPEDL_REG_OFFSET_MBST, IX_NPEDL_REG_RESET_MBST);
+ /* ...from NPE side */
+ error = npe_cpu_step(sc, IX_NPEDL_INSTR_RESET_MBOX, 0, 0);
if (error != 0) {
- DPRINTF(sc->sc_dev, "%s: cannot step (1), error %u\n",
- __func__, error);
- npe_cpu_step_restore(sc);
- return error;
+ DPRINTF(sc->sc_dev, "%s: cannot step (2), error %u\n",
+ __func__, error);
+ npe_cpu_step_restore(sc);
+ return error;
}
- }
-
>>> TRUNCATED FOR MAIL (1000 lines) <<<
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