PERFORCE change 112700 for review

[M. Warner Losh]

In message: <20070110091917.GF80390 at cicely12.cicely.de>
            Bernd Walter <ticso at cicely12.cicely.de> writes:
: On Wed, Jan 10, 2007 at 06:56:56AM +0000, Warner Losh wrote:
: > http://perforce.freebsd.org/chv.cgi?CH=112700
: > 
: > Change 112700 by imp at imp_lighthouse on 2007/01/10 06:56:33
: > 
: > 	MF FreeBSD-tsc-6: slow down spi bus enough to make the dataflash
: > 	parts reliable on read.  MCK / 2 is too fast.  I think MCK / 4
: > 	would work too, but MCK / 20 was rock solid.
: > 	
: > 	I think this works in the boot loader because we're running with
: > 	the caches off, slowing things down, but I am actually a bit
: > 	baffled.  Maybe I just have a bad board...
: 
: Mmm - you have a 'D' type flash, which allows 33MHz in low frequency
: mode.
: My 'C' type allows 33MHz as well.
: So in theory MCK/2 (30MHz) should work.
: Older 'B' type max out at 20MHz.
: I've just used flash access in the bootloader however.

Hmmm, MCK is 60MHz?  I thought it was 200MHz....

Warner

: > Affected files ...
: > 
: > .. //depot/projects/arm/src/sys/arm/at91/at91_spi.c#16 edit
: > 
: > Differences ...
: > 
: > ==== //depot/projects/arm/src/sys/arm/at91/at91_spi.c#16 (text+ko) ====
: > 
: > @@ -115,7 +115,7 @@
: >  	WR4(sc, SPI_MR, (0xf << 24) | SPI_MR_MSTR | SPI_MR_MODFDIS |
: >  	    (0xE << 16));
: >  
: > -	WR4(sc, SPI_CSR0, SPI_CSR_CPOL | (4 << 16) | (2 << 8));
: > +	WR4(sc, SPI_CSR0, SPI_CSR_CPOL | (4 << 16) | (20 << 8));
: >  	WR4(sc, SPI_CR, SPI_CR_SPIEN);
: >  
: >  	WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS);
: 
: -- 
: B.Walter                http://www.bwct.de      http://www.fizon.de
: bernd at bwct.de           info at bwct.de            support at fizon.de
: