PERFORCE change 108302 for review

[Oleksandr Tymoshenko]

http://perforce.freebsd.org/chv.cgi?CH=108302

Change 108302 by gonzo at gonzo_hq on 2006/10/23 10:19:04

	o Add TLBInvalid handler
	o Set exclusive bit in status register to zero, before 
	    calling for cpu_intr or trap. By doing that we guarantee
	    that TLBMiss exception will be handled only using 0x000
	    vector while TLBInvalid exception will be Handled by 
	    General Exception vector (0x180) and therefor we can separate
	    their handlers. Also it forces to use eret register to return
	    from trap in all handlers.

Affected files ...

.. //depot/projects/mips2/src/sys/mips/mips/exception.S#13 edit

Differences ...

==== //depot/projects/mips2/src/sys/mips/mips/exception.S#13 (text+ko) ====

@@ -23,7 +23,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $P4: //depot/projects/mips2/src/sys/mips/mips/exception.S#12 $
+ * $P4: //depot/projects/mips2/src/sys/mips/mips/exception.S#13 $
  */
 
 /*	$NetBSD: mipsX_subr.S,v 1.19 2005/12/11 12:18:09 christos Exp $	*/
@@ -168,8 +168,8 @@
 ExceptionHandlerTable:
 	.dword	GenericException	/* Int */
 	.dword	GenericException	/* TLBMod */
-	.dword	TLBMissVector		/* TLBL */
-	.dword	TLBMissVector		/* TLBS */
+	.dword	TLBInvalidVector	/* TLBL */
+	.dword	TLBInvalidVector	/* TLBS */
 	.dword	GenericException	/* AdEL */
 	.dword	GenericException	/* AdES */
 	.dword	GenericException	/* IBE */
@@ -259,6 +259,7 @@
 	and	k0, a1, MIPS3_CR_EXC_CODE
 	bnez	k0, 1f
 	move	a0, k1
+	mtc0	zero, MIPS_COP_0_STATUS
 
 	jal	cpu_intr
 	nop
@@ -276,7 +277,10 @@
 1:
 	mfc0	a1, MIPS_COP_0_CAUSE
 	mfc0	a2, MIPS_COP_0_BAD_VADDR
-
+	mtc0	zero, MIPS_COP_0_STATUS
+	COP0_SYNC
+	nop
+	nop
 	jal	trap
 	nop
 2:
@@ -313,7 +317,92 @@
 1:	.asciiz "Cache Vector"
 	.text
 
+LEAF(TLBInvalidVector)
+	.set noat
+	mfc0	k0, MIPS_COP_0_BAD_VADDR	# k0=badaddr
+	bgez	k0, GenericException
+	nop
+
+	/* VPN2 = (VA >> page_shift) / 2 */
+	la	k1, VM_MIN_KERNEL_ADDRESS
+	subu	k0, k0, k1
+	srl	k0, PAGE_SHIFT + 1
+
+	/* 
+	 * XXXMIPS: 
+	 * offset == VPN2 * sizeof(pt_entry_t)  * 2
+	 * dividing by 2 and multiplying by 2 we're 
+	 * getting even page number. MIPS TLB stuff 
+	 * works with couples of VP. 
+	 */
+	sll	k0, 2 + 1
+	la	k1, kptmap
+
+	/*
+	 * Find the page table, and index it.
+	 */
+	lw	k1, 0(k1)
+	addu	k1, k0
 
+	/*
+	 * EntryHi is already filled up with proper value
+	 */
+	tlbp
+	COP0_SYNC
+	and	k0, k0, 4	# Check odd/even 
+	nop
+	bne	k0, zero, KernTLBIOdd
+	nop
+
+	mfc0	k0, MIPS_COP_0_TLB_INDEX
+	nop
+	bltz	k0, tlbnotfound
+	lw	k0, 0(k1)
+	mtc0	k0, MIPS_COP_0_TLB_LO0
+	COP0_SYNC
+	and	k0, PG_V
+	beq	k0, zero, GenericException
+	lw	k0, 4(k1)
+	mfc0	k1, MIPS_COP_0_TLB_INDEX
+	nop
+	mtc0	k0, MIPS_COP_0_TLB_LO1
+	nop
+	tlbwi
+	COP0_SYNC
+	nop
+	nop
+	eret
+
+KernTLBIOdd:
+	mfc0	k0, MIPS_COP_0_TLB_INDEX
+	nop
+	bltz	k0, tlbnotfound
+	lw	k0, 0(k1)
+	mtc0	k0, MIPS_COP_0_TLB_LO1
+	COP0_SYNC
+	and	k0, PG_V
+	beq	k0, zero, GenericException
+	lw	k0, -4(k1)
+	mfc0	k1, MIPS_COP_0_TLB_INDEX
+	nop
+	mtc0	k0, MIPS_COP_0_TLB_LO0
+	nop
+	tlbwi
+	COP0_SYNC
+	nop
+	nop
+	eret
+
+tlbnotfound:
+	la	k0, panic
+	mtc0	k0, MIPS_COP_0_EXC_PC
+	la	a0, 2f
+	eret
+VEND(TLBInvalidVector)
+	.data
+2:	.asciiz "TLBInvalidVector"
+	.text
+
 /*
  * XXX kernel only.  For now that makes sense.
  */
@@ -323,7 +412,6 @@
 	mfc0	k0, MIPS_COP_0_BAD_VADDR	# k0=badaddr
 	bltz	k0, 5f				# k0<0 -> 5f (kernel fault)
 	nop
-
 6:
 	/* Userland */
 	lui	k1, %hi(segtab_active)	
@@ -364,7 +452,6 @@
 2:	.asciiz "TLBMissVector"
 	.text
 
-
 LEAF(KVATLBMiss)
 	.set noat
 	/*