PERFORCE change 101489 for review

[Warner Losh]

http://perforce.freebsd.org/chv.cgi?CH=101489

Change 101489 by imp at imp_lighthouse on 2006/07/13 21:42:16

	WIP for cognet

Affected files ...

.. //depot/projects/arm/src/sys/arm/at91/at91_tc.c#5 edit

Differences ...

==== //depot/projects/arm/src/sys/arm/at91/at91_tc.c#5 (text+ko) ====

@@ -66,10 +66,10 @@
 	int overflows;
 };
 
-#define RD4(counter, off) \
-	bus_read_4((counter)->sc->mem_res, (off) + (counter)->offset)
-#define WR4(counter, off, val) \
-	bus_write_4((counter)->sc->mem_res, (off) + (counter)->offset, (val))
+#define RD4(tc, off) \
+	bus_read_4((tc)->sc->mem_res, (off) + (tc)->offset)
+#define WR4(tc, off, val) \
+	bus_write_4((tc)->sc->mem_res, (off) + (tc)->offset, (val))
 #define RD4sc(sc, off) \
 	bus_read_4(sc->mem_res, (off))
 #define WR4sc(sc, off, val) \
@@ -104,9 +104,10 @@
 	at91_tc_get_timecount, /* get_timecount */
 	NULL, /* no poll_pps */
 	0xfffffu, /* counter_mask */
-	5000000, /* frequency */
+//	5000000, /* frequency */
+	60000000 / 8, /* frequency */
 	"5MHz", /* name */
-	20000 /* quality */
+	2000 /* quality */
 };
 #endif
 
@@ -142,6 +143,7 @@
 		// On the TSC board, we have 5MHz going into TIOA2.  Setup
 		// TC1's XC1 to use this.
 		WR4sc(sc, TC_BMR, TC_BMR_XC1_TIOA2);
+	printf("BMR: %x\n", RD4sc(sc, TC_BMR));
 #endif
 	for (i = 0; i < MAX_COUNTER; i++)
 		at91_tc_counter_init(sc, &sc->tc[i], i);
@@ -149,7 +151,7 @@
 	if (device_get_unit(dev) == 0) {
 		// XXX need cdev
 		// Init our timecounter.
-		at91_tc_tc = &sc->tc[0];
+		at91_tc_tc = &sc->tc[1];
 		tc_init(&at91_tc_timecounter);
 	}
 #endif
@@ -213,12 +215,13 @@
 #endif
 
 	tc->sc = sc;
+	printf("tc%d offset %x\n", unit, (uint32_t)tc->offset);
 #ifdef AT91_TSC
 	// Only TC1 is needed.  All others are disabled.
 	if (unit != 1 || device_get_unit(sc->dev) != 0) {
 #endif
+		WR4(tc, TC_IDR, 0xffffffff);
 		WR4(tc, TC_CCR, TC_CCR_CLKDIS);
-		WR4(tc, TC_IDR, 0xffffffff);
 		return;
 #ifdef AT91_TSC
 	}
@@ -234,14 +237,22 @@
 
 	// Setup TC1 into Capture Mode (WAVE=0), clocked by our external
 	// 5MHz, loading RA on rise and RB on falling edge
-	WR4(tc, TC_CMR, TC_CMR_XC1 | TC_CMR_BURST_NONE | TC_CMR_ETRGEDG_NONE |
+//	WR4(tc, TC_CMR, TC_CMR_XC1 | TC_CMR_BURST_NONE | TC_CMR_ETRGEDG_NONE |
+//	    TC_CMR_LDRA_RISE | TC_CMR_LDRB_FALL);
+	WR4(tc, TC_CMR, TC_CMR_TIMER_CLOCK2 | TC_CMR_BURST_NONE | TC_CMR_ETRGEDG_NONE |
 	    TC_CMR_LDRA_RISE | TC_CMR_LDRB_FALL);
-
+	printf("CMR: %x\n", RD4(tc, TC_CMR));
 	WR4(tc, TC_IDR, 0xffffffff);
 	WR4(tc, TC_IER, TC_SR_COVFS | TC_SR_LOVRS | TC_SR_LDRAS | TC_SR_LDRBS);
+	printf("IMR: %x\n", RD4(tc, TC_IMR));
 
 	// Now that we have ISR setup, we can enable clocks and go!
 	WR4(tc, TC_CCR, TC_CCR_SWTRG | TC_CCR_CLKEN);
+	{
+	    uint32_t last;
+	    last = RD4(tc, TC_CV);
+	    printf("Last is %x and %x SR %x\n", last, RD4(tc, TC_CV), RD4(tc, TC_SR));
+	}
 #endif
 }
 
@@ -252,9 +263,11 @@
 	struct at91_tc_counter *tc = argp;
 	uint32_t status;
 
+printf("Howdy!\n");
 	status = RD4(tc, TC_SR);
-	if (status & TC_SR_COVFS)
+	if (status & TC_SR_COVFS) {
 		tc->sc->overflows++;
+	}
 	if (status & TC_SR_LOVRS)
 		printf("Didn't read RA or RB in time\n");
 	if (status & TC_SR_LDRAS)