PERFORCE change 89900 for review
Warner Losh
imp at FreeBSD.org
Wed Jan 18 01:38:54 PST 2006
http://perforce.freebsd.org/chv.cgi?CH=89900
Change 89900 by imp at imp_plunger on 2006/01/18 09:36:49
Compile...
Affected files ...
.. //depot/projects/arm/src/sys/arm/at91/at91_twi.c#4 edit
.. //depot/projects/arm/src/sys/arm/at91/at91_twiio.h#2 edit
.. //depot/projects/arm/src/sys/arm/at91/at91_twireg.h#4 edit
Differences ...
==== //depot/projects/arm/src/sys/arm/at91/at91_twi.c#4 (text+ko) ====
@@ -28,6 +28,7 @@
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
+#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/mbuf.h>
@@ -37,6 +38,7 @@
#include <sys/rman.h>
#include <machine/bus.h>
+#include <arm/at91/at91rm92reg.h>
#include <arm/at91/at91_twireg.h>
#include <arm/at91/at91_twiio.h>
@@ -78,6 +80,7 @@
#define AT91_TWI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
#define AT91_TWI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
#define CDEV2SOFTC(dev) ((dev)->si_drv1)
+#define TWI_DEF_CLK 100000
static devclass_t at91_twi_devclass;
@@ -134,20 +137,20 @@
AT91_TWI_LOCK_DESTROY(sc);
goto out;
}
- sc->cdev = make_dev(at91_twi_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600,
+ sc->cdev = make_dev(&at91_twi_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600,
"twi%d", device_get_unit(dev));
if (sc->cdev == NULL) {
err = ENOMEM;
goto out;
}
sc->cdev->si_drv1 = sc;
- sc->cwgr = TWT_CWGR_CKDIV(1) |
- TWT_CWGR_CHDIV(TWT_CWGR_DIV(TWI_DEF_CLK)) |
- TWT_CWGR_CLDIV(TWT_CWGR_DIV(TWI_DEF_CLK));
+ sc->cwgr = TWI_CWGR_CKDIV(1) |
+ TWI_CWGR_CHDIV(TWI_CWGR_DIV(TWI_DEF_CLK)) |
+ TWI_CWGR_CLDIV(TWI_CWGR_DIV(TWI_DEF_CLK));
- WR4(sc, TWT_CR, TWI_CR_SWRST);
- WR4(sc, TWT_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
- WR4(sc, TWT_CWGR, sc->csgr);
+ WR4(sc, TWI_CR, TWI_CR_SWRST);
+ WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
+ WR4(sc, TWI_CWGR, sc->cwgr);
out:;
if (err)
at91_twi_deactivate(dev);
@@ -211,15 +214,15 @@
uint32_t status;
/* Reading the status also clears the interrupt */
- status = RD4(SC, TWI_SR);
+ status = RD4(sc, TWI_SR);
if (status == 0)
return;
AT91_TWI_LOCK(sc);
if (status & TWI_SR_RXRDY)
sc->flags |= RXRDY;
- if (statys & TWI_SR_TXCOMP)
+ if (status & TWI_SR_TXCOMP)
sc->flags |= TXCOMP;
- if (statys & TWI_SR_TXRDY)
+ if (status & TWI_SR_TXRDY)
sc->flags |= TXRDY;
AT91_TWI_UNLOCK(sc);
wakeup(sc);
@@ -235,8 +238,8 @@
AT91_TWI_LOCK(sc);
if (!(sc->flags & OPENED)) {
sc->flags |= OPENED;
- WR4(sc, TWI_IER, TWT_SR_TXCOMP | TWT_SR_RXRDY | TWT_SR_TXRDY |
- TWT_SR_OVRE | TWT_SR_UNRE | TWT_SR_NACK);
+ WR4(sc, TWI_IER, TWI_SR_TXCOMP | TWI_SR_RXRDY | TWI_SR_TXRDY |
+ TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_NACK);
}
AT91_TWI_UNLOCK(sc);
return (0);
@@ -250,8 +253,8 @@
sc = CDEV2SOFTC(dev);
AT91_TWI_LOCK(sc);
sc->flags &= ~OPENED;
- WR4(sc, TWI_IDR, TWT_SR_TXCOMP | TWT_SR_RXRDY | TWT_SR_TXRDY |
- TWT_SR_OVRE | TWT_SR_UNRE | TWT_SR_NACK);
+ WR4(sc, TWI_IDR, TWI_SR_TXCOMP | TWI_SR_RXRDY | TWI_SR_TXRDY |
+ TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_NACK);
AT91_TWI_UNLOCK(sc);
return (0);
}
@@ -260,20 +263,21 @@
static int
at91_twi_read_master(struct at91_twi_softc *sc, struct at91_twi_io *xfr)
{
+ uint8_t *walker;
uint8_t buffer[256];
size_t len;
- int err;
+ int err = 0;
if (xfr->xfer_len > sizeof(buffer))
return (EINVAL);
walker = buffer;
len = xfr->xfer_len;
- RD4(sc, TWT_RHR);
+ RD4(sc, TWI_RHR);
// Master mode, with the right address and interal addr size
- WR4(sc, TWT_MMR, TWT_MMR_IADRSZ(xfr->iadrsz) | TWT_MMR_MREAD |
- TWT_MMR_DADR(xfr->xadr));
- WR4(sc, TWT_IADR, xfr->iadr);
- WR4(sc, TWT_CR, TWT_CR_START);
+ WR4(sc, TWI_MMR, TWI_MMR_IADRSZ(xfr->iadrsz) | TWI_MMR_MREAD |
+ TWI_MMR_DADR(xfr->dadr));
+ WR4(sc, TWI_IADR, xfr->iadr);
+ WR4(sc, TWI_CR, TWI_CR_START);
while (len-- > 1) {
while (!(sc->flags & RXRDY)) {
err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twird",
@@ -284,7 +288,7 @@
sc->flags &= ~RXRDY;
*walker++ = RD4(sc, TWI_RHR) & 0xff;
}
- WR4(sc, TWT_CR, TWT_CR_STOP);
+ WR4(sc, TWI_CR, TWI_CR_STOP);
while (!(sc->flags & TXCOMP)) {
err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twird2", 0);
if (err)
@@ -303,6 +307,7 @@
static int
at91_twi_write_master(struct at91_twi_softc *sc, struct at91_twi_io *xfr)
{
+ uint8_t *walker;
uint8_t buffer[256];
size_t len;
int err;
@@ -320,11 +325,11 @@
xfr->xfer_buf = 0;
xfr->xfer_len = 1;
while (len--) {
- WR4(sc, TWT_MMR, TWT_MMR_IADRSZ(xfr->iadrsz) | TWT_MMR_MWRITE |
- TWT_MMR_DADR(xfr->xadr));
- WR4(sc, TWT_IADR, xfr->iadr++);
+ WR4(sc, TWI_MMR, TWI_MMR_IADRSZ(xfr->iadrsz) | TWI_MMR_MWRITE |
+ TWI_MMR_DADR(xfr->dadr));
+ WR4(sc, TWI_IADR, xfr->iadr++);
WR4(sc, TWI_THR, *walker++);
- WR4(sc, TWT_CR, TWT_CR_START);
+ WR4(sc, TWI_CR, TWI_CR_START);
/*
* If we get signal while waiting for TXRDY, make sure we
* try to stop this device
@@ -335,7 +340,7 @@
if (err)
break;
}
- WR4(sc, TWT_CR, TWT_CR_STOP);
+ WR4(sc, TWI_CR, TWI_CR_STOP);
if (err)
return (err);
while (!(sc->flags & TXCOMP)) {
@@ -373,7 +378,7 @@
{
case TWIIOCXFER:
{
- struct at91_twi_clock *xfr = (struct at91_twi_io *)data;
+ struct at91_twi_io *xfr = (struct at91_twi_io *)data;
switch (xfr->type)
{
case TWI_IO_READ_MASTER:
@@ -393,12 +398,12 @@
{
struct at91_twi_clock *twick = (struct at91_twi_clock *)data;
- sc->cwgr = TWT_CWGR_CKDIV(twick->ckdiv) |
- TWT_CWGR_CHDIV(TWT_CWGR_DIV(twick->high_rate)) |
- TWT_CWGR_CLDIV(TWT_CWGR_DIV(twick->low_rate));
- WR4(sc, TWT_CR, TWI_CR_SWRST);
- WR4(sc, TWT_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
- WR4(sc, TWT_CWGR, sc->csgr);
+ sc->cwgr = TWI_CWGR_CKDIV(twick->ckdiv) |
+ TWI_CWGR_CHDIV(TWI_CWGR_DIV(twick->high_rate)) |
+ TWI_CWGR_CLDIV(TWI_CWGR_DIV(twick->low_rate));
+ WR4(sc, TWI_CR, TWI_CR_SWRST);
+ WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
+ WR4(sc, TWI_CWGR, sc->cwgr);
break;
}
default:
==== //depot/projects/arm/src/sys/arm/at91/at91_twiio.h#2 (text+ko) ====
@@ -39,14 +39,14 @@
uint32_t iadr; /* Interbak addr */
size_t xfer_len; /* Size to transfer */
caddr_t xfer_buf; /* buffer for xfer */
-}
+};
struct at91_twi_clock
{
int ckdiv; /* Clock divider */
int high_rate; /* rate of clock high period */
int low_rate; /* rate of clock low period */
-}
+};
/** TWIIOCXFER: Do a two-wire transfer
*/
@@ -54,7 +54,7 @@
/** TWIIOCSETCLOCK: Sets the clocking parameters for this operation.
*/
-#define TWTIOCSETCLOCK _IOW('x', 2, struct at91_twi_clock)
+#define TWIIOCSETCLOCK _IOW('x', 2, struct at91_twi_clock)
#endif /* !_ARM_AT91_AT91_TWIIO_H */
==== //depot/projects/arm/src/sys/arm/at91/at91_twireg.h#4 (text+ko) ====
@@ -44,39 +44,39 @@
/* TWI_CR */
#define TWI_CR_START (1U << 0) /* Send a start */
-#define TWT_CR_STOP (1U << 1) /* Send a stop */
-#define TWT_CR_MSEN (1U << 2) /* Master Transfer Enable */
-#define TWT_CR_MSDIS (1U << 3) /* Master Transfer Disable */
-#define TWT_CR_SVEN (1U << 4) /* Slave Transfer Enable */
-#define TWT_CR_SVDIS (1U << 5) /* Slave Transfer Disable */
-#define TWT_CR_SWRST (1U << 7) /* Software Reset */
+#define TWI_CR_STOP (1U << 1) /* Send a stop */
+#define TWI_CR_MSEN (1U << 2) /* Master Transfer Enable */
+#define TWI_CR_MSDIS (1U << 3) /* Master Transfer Disable */
+#define TWI_CR_SVEN (1U << 4) /* Slave Transfer Enable */
+#define TWI_CR_SVDIS (1U << 5) /* Slave Transfer Disable */
+#define TWI_CR_SWRST (1U << 7) /* Software Reset */
/* TWI_MMR */
/* TWI_SMR */
-#define TWT_MMR_IADRSZ(n) ((n) << 8) /* Set size of transfer */
-#define TWT_MMR_MWRITE 0U /* Master Read Direction */
-#define TWT_MMR_MREAD (1U << 12) /* Master Read Direction */
-#define TWT_MMR_DADR(n) ((n) << 16) /* Device Address */
+#define TWI_MMR_IADRSZ(n) ((n) << 8) /* Set size of transfer */
+#define TWI_MMR_MWRITE 0U /* Master Read Direction */
+#define TWI_MMR_MREAD (1U << 12) /* Master Read Direction */
+#define TWI_MMR_DADR(n) ((n) << 16) /* Device Address */
/* TWI_CWGR */
-#define TWT_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */
-#define TWT_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */
-#define TWT_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */
-#define TWT_CWGR_DIV(rate) ((AT91C_MASTER_CLOCK / 4*(rate)) - 2)
+#define TWI_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */
+#define TWI_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */
+#define TWI_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */
+#define TWI_CWGR_DIV(rate) ((AT91C_MASTER_CLOCK /(4*(rate))) - 2)
/* TWI_SR */
/* TWI_IER */
/* TWI_IDR */
/* TWI_IMR */
-#define TWT_SR_TXCOMP (1U << 0) /* Transmission Completed */
-#define TWT_SR_RXRDY (1U << 1) /* Receive Holding Register Ready */
-#define TWT_SR_TXRDY (1U << 2) /* Transmit Holding Register Ready */
-#define TWT_SR_SVREAD (1U << 3) /* Slave Read */
-#define TWT_SR_SVACC (1U << 4) /* Slave Access */
-#define TWT_SR_GCACC (1U << 5) /* General Call Access */
-#define TWT_SR_OVRE (1U << 6) /* Overrun error */
-#define TWT_SR_UNRE (1U << 7) /* Underrun Error */
-#define TWT_SR_NACK (1U << 8) /* Not Acknowledged */
-#define TWT_SR_ARBLST (1U << 9) /* Arbitration Lost */
+#define TWI_SR_TXCOMP (1U << 0) /* Transmission Completed */
+#define TWI_SR_RXRDY (1U << 1) /* Receive Holding Register Ready */
+#define TWI_SR_TXRDY (1U << 2) /* Transmit Holding Register Ready */
+#define TWI_SR_SVREAD (1U << 3) /* Slave Read */
+#define TWI_SR_SVACC (1U << 4) /* Slave Access */
+#define TWI_SR_GCACC (1U << 5) /* General Call Access */
+#define TWI_SR_OVRE (1U << 6) /* Overrun error */
+#define TWI_SR_UNRE (1U << 7) /* Underrun Error */
+#define TWI_SR_NACK (1U << 8) /* Not Acknowledged */
+#define TWI_SR_ARBLST (1U << 9) /* Arbitration Lost */
#endif /* ARM_AT91_AT91_TWIREG_H */
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