PERFORCE change 89894 for review

[Warner Losh]

http://perforce.freebsd.org/chv.cgi?CH=89894

Change 89894 by imp at imp_hammer on 2006/01/18 09:03:16

	Add slave bits for completeness.  These aren't implemented on the
	AT91RM9200 or AT91SAM9261, so just leave them here for now.

Affected files ...

.. //depot/projects/arm/src/sys/arm/at91/at91_twireg.h#3 edit

Differences ...

==== //depot/projects/arm/src/sys/arm/at91/at91_twireg.h#3 (text+ko) ====

@@ -29,7 +29,7 @@
 
 #define TWI_CR		0x00		/* TWI Control Register */
 #define TWI_MMR		0x04		/* TWI Master Mode Register */
-		/*	0x08		   reserved */
+#define TWI_SMR		0x08		/* TWI Master Mode Register */
 #define TWI_IADR	0x0c		/* TWI Internal Address Register */
 #define TWI_CWGR	0x10		/* TWI Clock Waveform Generator Reg */
 		/*	0x14		   reserved */
@@ -45,12 +45,16 @@
 /* TWI_CR */
 #define TWI_CR_START	(1U << 0)	/* Send a start */
 #define TWT_CR_STOP	(1U << 1)	/* Send a stop */
-#define TWT_CR_MSEN	(1U << 2)	/* Master Send Enable */
-#define TWT_CR_MSDIS	(1U << 3)	/* Master Send Disable */
+#define TWT_CR_MSEN	(1U << 2)	/* Master Transfer Enable */
+#define TWT_CR_MSDIS	(1U << 3)	/* Master Transfer Disable */
+#define TWT_CR_SVEN	(1U << 4)	/* Slave Transfer Enable */
+#define TWT_CR_SVDIS	(1U << 5)	/* Slave Transfer Disable */
 #define TWT_CR_SWRST	(1U << 7)	/* Software Reset */
 
 /* TWI_MMR */
+/* TWI_SMR */
 #define TWT_MMR_IADRSZ(n) ((n) << 8)	/* Set size of transfer */
+#define TWT_MMR_MWRITE	0U		/* Master Read Direction */
 #define TWT_MMR_MREAD	(1U << 12)	/* Master Read Direction */
 #define TWT_MMR_DADR(n)	((n) << 16)	/* Device Address */
 
@@ -58,6 +62,7 @@
 #define TWT_CWGR_CKDIV(x) ((x) << 16)	/* Clock Divider */
 #define TWT_CWGR_CHDIV(x) ((x) << 8)	/* Clock High Divider */
 #define TWT_CWGR_CLDIV(x) ((x) << 0)	/* Clock Low Divider */
+#define TWT_CWGR_DIV(rate) ((AT91C_MASTER_CLOCK / 4*(rate)) - 2)
 
 /* TWI_SR */
 /* TWI_IER */
@@ -66,8 +71,12 @@
 #define TWT_SR_TXCOMP	(1U << 0)	/* Transmission Completed */
 #define TWT_SR_RXRDY	(1U << 1)	/* Receive Holding Register Ready */
 #define TWT_SR_TXRDY	(1U << 2)	/* Transmit Holding Register Ready */
+#define TWT_SR_SVREAD	(1U << 3)	/* Slave Read */
+#define TWT_SR_SVACC	(1U << 4)	/* Slave Access */
+#define TWT_SR_GCACC	(1U << 5)	/* General Call Access */
 #define TWT_SR_OVRE	(1U << 6)	/* Overrun error */
 #define TWT_SR_UNRE	(1U << 7)	/* Underrun Error */
 #define TWT_SR_NACK	(1U << 8)	/* Not Acknowledged */
+#define TWT_SR_ARBLST	(1U << 9)	/* Arbitration Lost */
 
 #endif /* ARM_AT91_AT91_TWIREG_H */