PERFORCE change 91863 for review
Kip Macy
kmacy at FreeBSD.org
Wed Feb 15 21:01:50 PST 2006
http://perforce.freebsd.org/chv.cgi?CH=91863
Change 91863 by kmacy at kmacy_storage:sun4v_work on 2006/02/16 05:01:43
re-add tsb.c in anticipation of tsb manipulation
MMU_SFSR no longer directly accessible - remove defines
don't bother with manipulating tsb virtually
remove tte bucket management - switching to 2 level page tables
remove pmap temporary mappings -
remove 256M hack for TSB
remove pmap_map_tsb
remove WATCHPOINT handling - not available
ifdef out soon to be re-written functionality in tsb.c
Affected files ...
.. //depot/projects/kmacy_sun4v/src/sys/conf/files.sun4v#4 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/cpu.h#3 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/param.h#3 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/tlb.h#2 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/tsb.h#2 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/dump_machdep.c#2 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/pmap.c#4 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/trap.c#2 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/tsb.c#2 edit
Differences ...
==== //depot/projects/kmacy_sun4v/src/sys/conf/files.sun4v#4 (text+ko) ====
@@ -73,6 +73,7 @@
sun4v/sun4v/sys_machdep.c standard
sun4v/sun4v/swtch.S standard
sun4v/sun4v/tlb.c standard
+sun4v/sun4v/tsb.c standard
sun4v/sun4v/tick.c standard
sun4v/sun4v/trap.c standard
sun4v/sun4v/uio_machdep.c standard
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/cpu.h#3 (text+ko) ====
@@ -85,6 +85,8 @@
#define UNIMPLEMENTED panic("%s not implemented", __FUNCTION__)
+#define likely(x) __builtin_expect((x),1)
+#define unlikely(x) __builtin_expect((x),0)
#endif
#endif /* !_MACHINE_CPU_H_ */
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/param.h#3 (text+ko) ====
@@ -52,7 +52,7 @@
#define _MACHINE_PARAM_H_
#ifndef MACHINE
-#define MACHINE "sparc64"
+#define MACHINE "sun4v"
#endif
#ifndef MACHINE_ARCH
#define MACHINE_ARCH "sparc64"
@@ -60,7 +60,7 @@
#define MID_MACHINE MID_SPARC64
#ifdef SMP
-#define MAXCPU 16
+#define MAXCPU 32
#else
#define MAXCPU 1
#endif /* SMP */
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/tlb.h#2 (text+ko) ====
@@ -75,24 +75,6 @@
#define TLB_CTX_USER_MIN (1)
#define TLB_CTX_USER_MAX (8192)
-#define MMU_SFSR_ASI_SHIFT (16)
-#define MMU_SFSR_FT_SHIFT (7)
-#define MMU_SFSR_E_SHIFT (6)
-#define MMU_SFSR_CT_SHIFT (4)
-#define MMU_SFSR_PR_SHIFT (3)
-#define MMU_SFSR_W_SHIFT (2)
-#define MMU_SFSR_OW_SHIFT (1)
-#define MMU_SFSR_FV_SHIFT (0)
-
-#define MMU_SFSR_ASI_SIZE (8)
-#define MMU_SFSR_FT_SIZE (6)
-#define MMU_SFSR_CT_SIZE (2)
-
-#define MMU_SFSR_GET_ASI(sfsr) \
- (((sfsr) >> MMU_SFSR_ASI_SHIFT) & ((1UL << MMU_SFSR_ASI_SIZE) - 1))
-#define MMU_SFSR_W (1UL << MMU_SFSR_W_SHIFT)
-#define MMU_SFSR_FV (1UL << MMU_SFSR_FV_SHIFT)
-
typedef void tlb_flush_user_t(void);
struct pmap;
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/tsb.h#2 (text+ko) ====
@@ -43,44 +43,26 @@
(TSB_BSHIFT - TSB_BUCKET_SHIFT - TTE_SHIFT)
#define TSB_BUCKET_MASK ((1 << TSB_BUCKET_ADDRESS_BITS) - 1)
-extern struct tte *tsb_kernel;
extern vm_size_t tsb_kernel_mask;
extern vm_size_t tsb_kernel_size;
extern vm_paddr_t tsb_kernel_phys;
-static __inline struct tte *
-tsb_vpntobucket(pmap_t pm, vm_offset_t vpn)
-{
- return (&pm->pm_tsb[(vpn & TSB_BUCKET_MASK) << TSB_BUCKET_SHIFT]);
-}
-static __inline struct tte *
-tsb_vtobucket(pmap_t pm, u_long sz, vm_offset_t va)
-{
- return (tsb_vpntobucket(pm, va >> TTE_PAGE_SHIFT(sz)));
-}
+typedef int (tsb_callback_t)(struct pmap *, struct pmap *, struct tte *, vm_offset_t);
-static __inline struct tte *
-tsb_kvpntotte(vm_offset_t vpn)
-{
- return (&tsb_kernel[vpn & tsb_kernel_mask]);
-}
+void tsb_set_tte(vm_paddr_t tsb_phys, vm_offset_t va, uint64_t tsb_tag, uint64_t tsb_data);
-static __inline struct tte *
-tsb_kvtotte(vm_offset_t va)
-{
- return (tsb_kvpntotte(va >> PAGE_SHIFT));
-}
+struct tte *tsb_tte_lookup(pmap_t pm, vm_offset_t va);
-typedef int (tsb_callback_t)(struct pmap *, struct pmap *, struct tte *,
- vm_offset_t);
+void tsb_tte_remove(struct tte *stp);
-struct tte *tsb_tte_lookup(pmap_t pm, vm_offset_t va);
-void tsb_tte_remove(struct tte *stp);
-struct tte *tsb_tte_enter(pmap_t pm, vm_page_t m, vm_offset_t va, u_long sz,
+struct tte *tsb_tte_enter(pmap_t pm, vm_page_t m, vm_offset_t va, u_long sz,
u_long data);
-void tsb_tte_local_remove(struct tte *tp);
-void tsb_foreach(pmap_t pm1, pmap_t pm2, vm_offset_t start, vm_offset_t end,
- tsb_callback_t *callback);
+
+void tsb_tte_local_remove(struct tte *tp);
+
+void tsb_foreach(pmap_t pm1, pmap_t pm2, vm_offset_t start, vm_offset_t end,
+ tsb_callback_t *callback);
+
#endif /* !_MACHINE_TSB_H_ */
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/dump_machdep.c#2 (text+ko) ====
@@ -204,7 +204,6 @@
hdr.dh_hdr_size = hdrsize;
hdr.dh_tsb_pa = tsb_kernel_phys;
hdr.dh_tsb_size = tsb_kernel_size;
- hdr.dh_tsb_mask = tsb_kernel_mask;
hdr.dh_nregions = nreg;
if (buf_write(di, (char *)&hdr, sizeof(hdr)) != 0)
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/pmap.c#4 (text+ko) ====
@@ -34,6 +34,7 @@
#include <vm/vm_pageout.h>
#include <vm/vm_pager.h>
+#include <machine/cpu.h>
#include <machine/cache.h>
#include <machine/frame.h>
#include <machine/instr.h>
@@ -79,11 +80,6 @@
int sparc64_nmemreg;
-static vm_offset_t pmap_idle_map;
-static vm_offset_t pmap_temp_map_1;
-static vm_offset_t pmap_temp_map_2;
-
-
/*
* First and last available kernel virtual addresses.
*/
@@ -92,10 +88,8 @@
vm_offset_t kernel_vm_end;
vm_offset_t vm_max_kernel_address;
-struct tte *tsb_kernel;
-vm_size_t tsb_kernel_mask;
-vm_size_t tsb_kernel_size;
-vm_paddr_t tsb_kernel_phys;
+
+
/*
* Kernel pmap.
@@ -121,6 +115,8 @@
*/
#define PMAP_TSB_THRESH ((TSB_SIZE / 2) * PAGE_SIZE)
+#define PANIC_IF(exp) if (unlikely(exp)) {panic("%s: %s:%d", #exp, __FILE__, __LINE__);}
+
/*
* Kernel MMU interface
*/
@@ -175,22 +171,10 @@
vm_paddr_t pa;
int i;
- /* XXX start from 32MB offset for really large requests */
printf("looking for size %lx\n", size);
size = round_page(size);
- i = 0;
-#ifndef NO_SUN4V_HACK
- /* set us up to return memory on a 256M boundary */
- if (size > PAGE_SIZE_4M) {
- i = phys_avail[1]; /* current end */
- phys_avail[1] = PAGE_SIZE_256M;
- phys_avail[2] = PAGE_SIZE_256M;
- phys_avail[3] = i;
- i = 2;
- }
-#endif
- for (; phys_avail[i + 1] != 0; i += 2) {
+ for (i = 0; phys_avail[i + 1] != 0; i += 2) {
if (phys_avail[i + 1] - phys_avail[i] < size)
continue;
pa = phys_avail[i];
@@ -224,17 +208,12 @@
pmap_bootstrap(vm_offset_t ekva)
{
struct pmap *pm;
- struct tte *tp;
- vm_offset_t off;
- vm_offset_t va;
+ vm_offset_t off, va;
vm_paddr_t pa;
- vm_size_t physsz;
- vm_size_t virtsz;
- ihandle_t pmem;
- ihandle_t vmem;
- int sz;
- int i;
- int j;
+ vm_size_t physsz, virtsz, scrubbed;
+ ihandle_t pmem, vmem;
+ int i, sz, j;
+
/*
* Find out what physical memory is available from the prom and
* initialize the phys_avail array. This must be done before
@@ -282,10 +261,9 @@
* Calculate the size of kernel virtual memory, and the size and mask
* for the kernel tsb.
*/
- virtsz = roundup(physsz, PAGE_SIZE_256M << (PAGE_SHIFT - TTE_SHIFT));
+ virtsz = roundup(physsz, PAGE_SIZE_4M << (PAGE_SHIFT - TTE_SHIFT));
vm_max_kernel_address = VM_MIN_KERNEL_ADDRESS + virtsz;
- tsb_kernel_size = virtsz >> (PAGE_SHIFT - TTE_SHIFT);
- tsb_kernel_mask = (tsb_kernel_size >> TTE_SHIFT) - 1;
+ tsb_kernel_size = PAGE_SIZE_4M;
/*
* Allocate the kernel tsb and lock it in the tlb.
@@ -294,13 +272,7 @@
if (pa & PAGE_MASK_4M)
panic("pmap_bootstrap: tsb unaligned\n");
tsb_kernel_phys = pa;
- tsb_kernel = (struct tte *)(VM_MIN_KERNEL_ADDRESS - tsb_kernel_size);
- hv_cnputchar('B');
- pmap_map_tsb();
- hv_cnputchar('C');
- printf("bzeroing\n");
- bzero(tsb_kernel, tsb_kernel_size);
- printf("bzeroed\n");
+ PANIC_IF(hv_mem_scrub(tsb_kernel_phys, tsb_kernel_size, &scrubbed));
/*
* Allocate and map the message buffer.
*/
@@ -308,45 +280,6 @@
msgbufp = (struct msgbuf *)TLB_PHYS_TO_DIRECT(msgbuf_phys);
/*
- * Patch the virtual address and the tsb mask into the trap table.
- */
-
-#define SETHI(rd, imm22) \
- (EIF_OP(IOP_FORM2) | EIF_F2_RD(rd) | EIF_F2_OP2(INS0_SETHI) | \
- EIF_IMM((imm22) >> 10, 22))
-#define OR_R_I_R(rd, imm13, rs1) \
- (EIF_OP(IOP_MISC) | EIF_F3_RD(rd) | EIF_F3_OP3(INS2_OR) | \
- EIF_F3_RS1(rs1) | EIF_F3_I(1) | EIF_IMM(imm13, 13))
-
-#define PATCH(addr) do { \
- if (addr[0] != SETHI(IF_F2_RD(addr[0]), 0x0) || \
- addr[1] != OR_R_I_R(IF_F3_RD(addr[1]), 0x0, IF_F3_RS1(addr[1])) || \
- addr[2] != SETHI(IF_F2_RD(addr[2]), 0x0)) \
- panic("pmap_boostrap: patched instructions have changed"); \
- addr[0] |= EIF_IMM((tsb_kernel_mask) >> 10, 22); \
- addr[1] |= EIF_IMM(tsb_kernel_mask, 10); \
- addr[2] |= EIF_IMM(((vm_offset_t)tsb_kernel) >> 10, 22); \
- flush(addr); \
- flush(addr + 1); \
- flush(addr + 2); \
-} while (0)
-
- /*
- * Enter fake 8k pages for the 4MB kernel pages, so that
- * pmap_kextract() will work for them.
- */
- for (i = 0; i < kernel_tlb_slots; i++) {
- pa = kernel_tlbs[i].te_pa;
- va = kernel_tlbs[i].te_va;
- for (off = 0; off < PAGE_SIZE_4M; off += PAGE_SIZE) {
- tp = tsb_kvtotte(va + off);
- tp->tte_vpn = TV_VPN(va + off, TS_8K);
- tp->tte_data = VTD_V | VTD_PA(pa + off) | VTD_REF |
- VTD_SW | VTD_CP | VTD_CV | VTD_P | VTD_W | VTD_8K;
- }
- }
-
- /*
* Set the start and end of kva. The kernel is loaded at the first
* available 4 meg super page, so round up to the end of the page.
*/
@@ -355,16 +288,6 @@
kernel_vm_end = vm_max_kernel_address;
/*
- * Allocate kva space for temporary mappings.
- */
- pmap_idle_map = virtual_avail;
- virtual_avail += PAGE_SIZE * DCACHE_COLORS;
- pmap_temp_map_1 = virtual_avail;
- virtual_avail += PAGE_SIZE * DCACHE_COLORS;
- pmap_temp_map_2 = virtual_avail;
- virtual_avail += PAGE_SIZE * DCACHE_COLORS;
-
- /*
* Allocate a kernel stack with guard page for thread0 and map it into
* the kernel tsb. We must ensure that the virtual address is coloured
* properly, since we're allocating from phys_avail so the memory won't
@@ -382,10 +305,7 @@
for (i = 0; i < KSTACK_PAGES; i++) {
pa = kstack0_phys + i * PAGE_SIZE;
va = kstack0 + i * PAGE_SIZE;
- tp = tsb_kvtotte(va);
- tp->tte_vpn = TV_VPN(va, TS_8K);
- tp->tte_data = VTD_V | VTD_PA(pa) | VTD_REF | VTD_SW |
- VTD_CP | VTD_CV | VTD_P | VTD_W | VTD_8K;
+ UNIMPLEMENTED;
}
/*
@@ -422,12 +342,10 @@
for (off = 0; off < translations[i].om_size;
off += PAGE_SIZE) {
va = translations[i].om_start + off;
- tp = tsb_kvtotte(va);
- tp->tte_vpn = TV_VPN(va, TS_8K);
- tp->tte_data =
- ((translations[i].om_tte &
- ~(TD_SOFT_MASK << TD_SOFT_SHIFT)) | TD_EXEC) +
+ pa = ((translations[i].om_tte &
+ ~(TD_SOFT_MASK << TD_SOFT_SHIFT)) | TD_EXEC) +
off;
+ tsb_set_tte(tsb_kernel_phys, va, TV_VPN(va, TS_8K), pa);
}
}
@@ -614,45 +532,6 @@
return (0);
}
-void
-pmap_map_tsb(void)
-{
- vm_offset_t va;
- vm_paddr_t pa;
- u_long data;
- u_long s;
- int i, ret;
-
- s = intr_disable();
-
- /*
- * Map a 256MB TSB page
- */
- for (i = 0; i < tsb_kernel_size; i += 64*PAGE_SIZE_4M) {
- va = (vm_offset_t)tsb_kernel + i;
- pa = tsb_kernel_phys + i;
- data = VTD_V | VTD_PA(pa) | VTD_CP | VTD_CV | VTD_P | VTD_W | VTD_256M;
- printf("va: %lx tte: %lx\n", va, data);
- ret = hv_mmu_map_perm_addr((char *)va, 0, data, MAP_DTLB);
- if (ret)
-#ifdef notyet
- panic("hv_mmu_map_perm_addr failed: %d\n", ret);
-#else
- printf("hv_mmu_map_perm_addr failed: %d\n", ret);
-#endif
- }
-#ifdef notyet
- /* XXX SUN4V_FIXME */
- /*
- * Set the secondary context to be the kernel context (needed for
- * fp block operations in the kernel and the cache code).
- */
- stxa(AA_DMMU_SCXR, ASI_DMMU, TLB_CTX_KERNEL);
- membar(Sync);
-#endif
- intr_restore(s);
-}
-
int
pmap_mincore(pmap_t pmap, vm_offset_t addr)
{
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/trap.c#2 (text+ko) ====
@@ -312,12 +312,6 @@
error = (kdb_trap(tf->tf_type, 0, tf) == 0);
TF_DONE(tf);
break;
-#ifdef notyet
- case T_PA_WATCHPOINT:
- case T_VA_WATCHPOINT:
- error = db_watch_trap(tf);
- break;
-#endif
#endif
case T_DATA_MISS:
case T_DATA_PROTECTION:
@@ -326,6 +320,7 @@
break;
case T_DATA_EXCEPTION:
case T_MEM_ADDRESS_NOT_ALIGNED:
+#ifdef notyet
if ((tf->tf_sfsr & MMU_SFSR_FV) != 0 &&
MMU_SFSR_GET_ASI(tf->tf_sfsr) == ASI_AIUP) {
if (tf->tf_tpc >= (u_long)copy_nofault_begin &&
@@ -343,26 +338,11 @@
break;
}
}
+#endif
error = 1;
break;
case T_DATA_ERROR:
- /*
- * handle PCI poke/peek as per UltraSPARC IIi
- * User's Manual 16.2.1.
- */
-#define MEMBARSYNC_INST ((u_int32_t)0x8143e040)
- if (tf->tf_tpc > (u_long)fas_nofault_begin &&
- tf->tf_tpc < (u_long)fas_nofault_end &&
- *(u_int32_t *)tf->tf_tpc == MEMBARSYNC_INST &&
- ((u_int32_t *)tf->tf_tpc)[-2] == MEMBARSYNC_INST) {
- cache_flush();
- cache_enable();
- tf->tf_tpc = (u_long)fas_fault;
- tf->tf_tnpc = tf->tf_tpc + 4;
- error = 0;
- break;
- }
-#undef MEMBARSYNC_INST
+ UNIMPLEMENTED;
error = 1;
break;
default:
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/tsb.c#2 (text+ko) ====
@@ -74,19 +74,18 @@
PMAP_STATS_VAR(tsb_nenter_u_oc);
PMAP_STATS_VAR(tsb_nforeach);
-struct tte *tsb_kernel;
-vm_size_t tsb_kernel_mask;
vm_size_t tsb_kernel_size;
vm_paddr_t tsb_kernel_phys;
+
struct tte *
tsb_tte_lookup(pmap_t pm, vm_offset_t va)
{
+#ifdef notyet
struct tte *bucket;
struct tte *tp;
u_long sz;
u_int i;
-
if (pm == kernel_pmap) {
PMAP_STATS_INC(tsb_nlookup_k);
tp = tsb_kvtotte(va);
@@ -104,12 +103,14 @@
}
}
}
+#endif
return (NULL);
}
struct tte *
tsb_tte_enter(pmap_t pm, vm_page_t m, vm_offset_t va, u_long sz, u_long data)
{
+#if 0
struct tte *bucket;
struct tte *rtp;
struct tte *tp;
@@ -186,6 +187,8 @@
tp->tte_data = data;
return (tp);
+#endif
+ return (0);
}
/*
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