PERFORCE change 91785 for review
Kip Macy
kmacy at FreeBSD.org
Tue Feb 14 21:31:08 PST 2006
http://perforce.freebsd.org/chv.cgi?CH=91785
Change 91785 by kmacy at kmacy_storage:sun4v_work on 2006/02/15 05:30:42
fix all link-time errors except for those remaining in exception.S
Affected files ...
.. //depot/projects/kmacy_sun4v/src/sys/conf/files.sun4v#3 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/conf/GENERIC#2 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/bus.h#2 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/cpufunc.h#2 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/pmap.h#2 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/bus_machdep.c#2 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/exception.S#3 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/hcall.S#2 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/interrupt.S#3 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/machdep.c#4 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/pmap.c#3 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/swtch.S#3 edit
.. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/vm_machdep.c#2 edit
Differences ...
==== //depot/projects/kmacy_sun4v/src/sys/conf/files.sun4v#3 (text+ko) ====
@@ -51,6 +51,7 @@
sun4v/sun4v/eeprom.c optional eeprom ebus | eeprom fhc | \
eeprom sbus
sun4v/sun4v/gdb_machdep.c optional gdb
+sun4v/sun4v/hcall.S standard
sun4v/sun4v/identcpu.c standard
sun4v/sun4v/in_cksum.c optional inet
sun4v/sun4v/interrupt.S standard no-obj
@@ -71,6 +72,7 @@
sun4v/sun4v/support.S standard
sun4v/sun4v/sys_machdep.c standard
sun4v/sun4v/swtch.S standard
+sun4v/sun4v/tlb.c standard
sun4v/sun4v/tick.c standard
sun4v/sun4v/trap.c standard
sun4v/sun4v/uio_machdep.c standard
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/conf/GENERIC#2 (text+ko) ====
@@ -116,7 +116,7 @@
# Builtin hardware
#device auxio # auxiliary I/O device
#device clkbrd # Clock Board (blinkenlight on Sun Exx00)
-#device genclock # Generic clock interface
+device genclock # Generic clock interface
#device eeprom # eeprom (really a front-end for the MK48Txx)
#device mk48txx # Mostek MK48Txx clocks
#device rtc # rtc (really a front-end for the MC146818)
@@ -172,10 +172,10 @@
#device udbp # USB Double Bulk Pipe devices
#device ugen # Generic
#device uhid # "Human Interface Devices"
-device ukbd # Keyboard
+#device ukbd # Keyboard
#device ulpt # Printer
#device umass # Disks/Mass storage - Requires scbus and da
-device ums # Mouse
+#device ums # Mouse
#device urio # Diamond Rio 500 MP3 player
#device uscanner # Scanners
# USB Ethernet, requires mii
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/bus.h#2 (text+ko) ====
@@ -216,32 +216,36 @@
bus_space_read_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
+
__BUS_DEBUG_ACCESS(h, o, "read", 1);
- return (lduba_nc((caddr_t)(h + o), bus_type_asi[t->bst_type]));
+ return (0);
}
static __inline uint16_t
bus_space_read_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
+
__BUS_DEBUG_ACCESS(h, o, "read", 2);
- return (lduha_nc((caddr_t)(h + o), bus_type_asi[t->bst_type]));
+ return (0);
}
static __inline uint32_t
bus_space_read_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
+
__BUS_DEBUG_ACCESS(h, o, "read", 4);
- return (lduwa_nc((caddr_t)(h + o), bus_type_asi[t->bst_type]));
+ return (0);
}
static __inline uint64_t
bus_space_read_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
+
__BUS_DEBUG_ACCESS(h, o, "read", 8);
- return (ldxa_nc((caddr_t)(h + o), bus_type_asi[t->bst_type]));
+ return (0);
}
static __inline void
@@ -285,8 +289,8 @@
uint8_t v)
{
+
__BUS_DEBUG_ACCESS(h, o, "write", 1);
- stba_nc((caddr_t)(h + o), bus_type_asi[t->bst_type], v);
}
static __inline void
@@ -294,8 +298,8 @@
uint16_t v)
{
+
__BUS_DEBUG_ACCESS(h, o, "write", 2);
- stha_nc((caddr_t)(h + o), bus_type_asi[t->bst_type], v);
}
static __inline void
@@ -303,8 +307,8 @@
uint32_t v)
{
+
__BUS_DEBUG_ACCESS(h, o, "write", 4);
- stwa_nc((caddr_t)(h + o), bus_type_asi[t->bst_type], v);
}
static __inline void
@@ -312,8 +316,8 @@
uint64_t v)
{
+
__BUS_DEBUG_ACCESS(h, o, "write", 8);
- stxa_nc((caddr_t)(h + o), bus_type_asi[t->bst_type], v);
}
static __inline void
@@ -520,32 +524,36 @@
bus_space_read_stream_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
+
__BUS_DEBUG_ACCESS(h, o, "read stream", 1);
- return (lduba_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type]));
+ return (0);
}
static __inline uint16_t
bus_space_read_stream_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
+
__BUS_DEBUG_ACCESS(h, o, "read stream", 2);
- return (lduha_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type]));
+ return (0);
}
static __inline uint32_t
bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
+
__BUS_DEBUG_ACCESS(h, o, "read stream", 4);
- return (lduwa_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type]));
+ return (0);
}
static __inline uint64_t
bus_space_read_stream_8(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o)
{
+
__BUS_DEBUG_ACCESS(h, o, "read stream", 8);
- return (ldxa_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type]));
+ return (0);
}
static __inline void
@@ -589,6 +597,7 @@
uint8_t v)
{
+
__BUS_DEBUG_ACCESS(h, o, "write stream", 1);
stba_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type], v);
}
@@ -598,8 +607,8 @@
uint16_t v)
{
+
__BUS_DEBUG_ACCESS(h, o, "write stream", 2);
- stha_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type], v);
}
static __inline void
@@ -607,8 +616,8 @@
uint32_t v)
{
+
__BUS_DEBUG_ACCESS(h, o, "write stream", 4);
- stwa_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type], v);
}
static __inline void
@@ -616,8 +625,8 @@
uint64_t v)
{
+
__BUS_DEBUG_ACCESS(h, o, "write stream", 8);
- stxa_nc((caddr_t)(h + o), bus_stream_asi[t->bst_type], v);
}
static __inline void
@@ -828,8 +837,9 @@
u_int8_t *a)
{
+
__BUS_DEBUG_ACCESS(h, o, "peek", 1);
- return (fasword8(bus_type_asi[t->bst_type], (caddr_t)(h + o), a));
+ return (0);
}
static __inline int
@@ -837,8 +847,9 @@
u_int16_t *a)
{
+
__BUS_DEBUG_ACCESS(h, o, "peek", 2);
- return (fasword16(bus_type_asi[t->bst_type], (caddr_t)(h + o), a));
+ return (0);
}
static __inline int
@@ -846,8 +857,9 @@
u_int32_t *a)
{
+
__BUS_DEBUG_ACCESS(h, o, "peek", 4);
- return (fasword32(bus_type_asi[t->bst_type], (caddr_t)(h + o), a));
+ return (0);
}
/* Back-compat functions for old ISA drivers */
@@ -856,7 +868,7 @@
extern bus_space_tag_t isa_mem_bt;
extern bus_space_handle_t isa_mem_hdl;
-#define inb(o) bus_space_read_1(isa_io_bt, isa_io_hdl, o)
+ #define inb(o) bus_space_read_1(isa_io_bt, isa_io_hdl, o)
#define inw(o) bus_space_read_2(isa_io_bt, isa_io_hdl, o)
#define inl(o) bus_space_read_4(isa_io_bt, isa_io_hdl, o)
#define outb(o, v) bus_space_write_1(isa_io_bt, isa_io_hdl, o, v)
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/cpufunc.h#2 (text+ko) ====
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/pmap.h#2 (text+ko) ====
@@ -83,7 +83,6 @@
void pmap_kremove(vm_offset_t);
void pmap_kenter_flags(vm_offset_t va, vm_paddr_t pa, u_long flags);
void pmap_kremove_flags(vm_offset_t va);
-boolean_t pmap_page_is_mapped(vm_page_t m);
int pmap_cache_enter(vm_page_t m, vm_offset_t va);
void pmap_cache_remove(vm_page_t m, vm_offset_t va);
@@ -116,6 +115,8 @@
return (1);
}
+#define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.tte_list))
+
#ifdef PMAP_STATS
SYSCTL_DECL(_debug_pmap_stats);
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/bus_machdep.c#2 (text+ko) ====
@@ -129,25 +129,6 @@
static void nexus_bus_barrier(bus_space_tag_t, bus_space_handle_t,
bus_size_t, bus_size_t, int);
-/* ASI's for bus access. */
-int bus_type_asi[] = {
- ASI_PHYS_BYPASS_EC_WITH_EBIT, /* UPA */
- ASI_PHYS_BYPASS_EC_WITH_EBIT, /* SBUS */
- ASI_PHYS_BYPASS_EC_WITH_EBIT_L, /* PCI configuration space */
- ASI_PHYS_BYPASS_EC_WITH_EBIT_L, /* PCI memory space */
- ASI_PHYS_BYPASS_EC_WITH_EBIT_L, /* PCI I/O space */
- 0
-};
-
-int bus_stream_asi[] = {
- ASI_PHYS_BYPASS_EC_WITH_EBIT, /* UPA */
- ASI_PHYS_BYPASS_EC_WITH_EBIT, /* SBUS */
- ASI_PHYS_BYPASS_EC_WITH_EBIT, /* PCI configuration space */
- ASI_PHYS_BYPASS_EC_WITH_EBIT, /* PCI memory space */
- ASI_PHYS_BYPASS_EC_WITH_EBIT, /* PCI I/O space */
- 0
-};
-
/*
* Convenience function for manipulating driver locks from busdma (during
* busdma_swi, for example). Drivers that don't provide their own locks
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/exception.S#3 (text+ko) ====
@@ -276,13 +276,6 @@
ldx [ASP_REG + 0], %g1 ; \
inc 16, ASP_REG
-/*
- * For certain faults we need to clear the sfsr mmu register before returning.
- */
-#define RSF_CLR_SFSR \
- wr %g0, ASI_DMMU, %asi ; \
- stxa %g0, [%g0 + AA_DMMU_SFSR] %asi
-
#define RSF_XOR(off) ((0x80 - off) - 1)
/*
@@ -484,40 +477,50 @@
.endm
.macro tl0_insn_excptn
- wrpr %g0, PSTATE_ALT, %pstate
- wr %g0, ASI_IMMU, %asi
- rdpr %tpc, %g3
- ldxa [%g0 + AA_IMMU_SFSR] %asi, %g4
- stxa %g0, [%g0 + AA_IMMU_SFSR] %asi
- membar #Sync
- ba %xcc, tl0_sfsr_trap
- mov T_INSTRUCTION_EXCEPTION, %g2
.align 32
.endm
.macro tl0_data_excptn
- wrpr %g0, PSTATE_ALT, %pstate
- wr %g0, ASI_DMMU, %asi
- ldxa [%g0 + AA_DMMU_SFAR] %asi, %g3
- ldxa [%g0 + AA_DMMU_SFSR] %asi, %g4
- stxa %g0, [%g0 + AA_DMMU_SFSR] %asi
- membar #Sync
- ba %xcc, tl0_sfsr_trap
- mov T_DATA_EXCEPTION, %g2
.align 32
.endm
.macro tl0_align
- wr %g0, ASI_DMMU, %asi
- ldxa [%g0 + AA_DMMU_SFAR] %asi, %g3
- ldxa [%g0 + AA_DMMU_SFSR] %asi, %g4
- stxa %g0, [%g0 + AA_DMMU_SFSR] %asi
- membar #Sync
- ba %xcc, tl0_sfsr_trap
- mov T_MEM_ADDRESS_NOT_ALIGNED, %g2
+ .align 32
+ .endm
+
+ .macro cpu_mondo
+ .align 32
+ .endm
+
+ .macro dev_mondo
+ .align 32
+ .endm
+
+ .macro resumable_error
+ .align 32
+ .endm
+
+ .macro unresumable_error
+ .align 32
+ .endm
+
+ .macro spill_n_normal type
+ .align 32
+ .endm
+
+ .macro spill_n_other type
+ .align 32
+ .endm
+
+ .macro fill_n_normal type
.align 32
.endm
+ .macro fill_n_other type
+ .align 32
+ .endm
+
+
ENTRY(tl0_sfsr_trap)
tl0_split
clr %o1
@@ -563,121 +566,7 @@
INTR_LEVEL(0)
.endm
- .macro intr_vector
- ldxa [%g0] ASI_INTR_RECEIVE, %g1
- andcc %g1, IRSR_BUSY, %g0
- bnz,a,pt %xcc, intr_vector
- nop
- sir
- .align 32
- .endm
-
.macro tl0_immu_miss
- /*
- * Load the virtual page number and context from the tag access
- * register. We ignore the context.
- */
- wr %g0, ASI_IMMU, %asi
- ldxa [%g0 + AA_IMMU_TAR] %asi, %g1
-
- /*
- * Initialize the page size walker.
- */
- mov TS_MIN, %g2
-
- /*
- * Loop over all supported page sizes.
- */
-
- /*
- * Compute the page shift for the page size we are currently looking
- * for.
- */
-1: add %g2, %g2, %g3
- add %g3, %g2, %g3
- add %g3, PAGE_SHIFT, %g3
-
- /*
- * Extract the virtual page number from the contents of the tag
- * access register.
- */
- srlx %g1, %g3, %g3
-
- /*
- * Compute the tte bucket address.
- */
- ldxa [%g0 + AA_IMMU_TSB] %asi, %g5
- and %g3, TSB_BUCKET_MASK, %g4
- sllx %g4, TSB_BUCKET_SHIFT + TTE_SHIFT, %g4
- add %g4, %g5, %g4
-
- /*
- * Compute the tte tag target.
- */
- sllx %g3, TV_SIZE_BITS, %g3
- or %g3, %g2, %g3
-
- /*
- * Loop over the ttes in this bucket
- */
-
- /*
- * Load the tte. Note that this instruction may fault, clobbering
- * the contents of the tag access register, %g5, %g6, and %g7. We
- * do not use %g5, and %g6 and %g7 are not used until this instruction
- * completes successfully.
- */
-2: ldda [%g4] ASI_NUCLEUS_QUAD_LDD, %g6 /*, %g7 */
-
- /*
- * Check that its valid and executable and that the tte tags match.
- */
- brgez,pn %g7, 3f
- andcc %g7, TD_EXEC, %g0
- bz,pn %xcc, 3f
- cmp %g3, %g6
- bne,pn %xcc, 3f
- EMPTY
-
- /*
- * We matched a tte, load the tlb.
- */
-
- /*
- * Set the reference bit, if it's currently clear.
- */
- andcc %g7, TD_REF, %g0
- bz,a,pn %xcc, tl0_immu_miss_set_ref
- nop
-
- /*
- * Load the tte tag and data into the tlb and retry the instruction.
- */
- stxa %g1, [%g0 + AA_IMMU_TAR] %asi
- stxa %g7, [%g0] ASI_ITLB_DATA_IN_REG
- retry
-
- /*
- * Advance to the next tte in this bucket, and check the low bits
- * of the bucket pointer to see if we've finished the bucket.
- */
-3: add %g4, 1 << TTE_SHIFT, %g4
- andcc %g4, (1 << (TSB_BUCKET_SHIFT + TTE_SHIFT)) - 1, %g0
- bnz,pt %xcc, 2b
- EMPTY
-
- /*
- * See if we just checked the largest page size, and advance to the
- * next one if not.
- */
- cmp %g2, TS_MAX
- bne,pt %xcc, 1b
- add %g2, 1, %g2
-
- /*
- * Not in user tsb, call c code.
- */
- ba,a %xcc, tl0_immu_miss_trap
.align 128
.endm
@@ -1202,14 +1091,6 @@
END(tl0_fp_restore)
.macro tl1_insn_excptn
- wrpr %g0, PSTATE_ALT, %pstate
- wr %g0, ASI_IMMU, %asi
- rdpr %tpc, %g3
- ldxa [%g0 + AA_IMMU_SFSR] %asi, %g4
- stxa %g0, [%g0 + AA_IMMU_SFSR] %asi
- membar #Sync
- ba %xcc, tl1_insn_exceptn_trap
- mov T_INSTRUCTION_EXCEPTION | T_KERNEL, %g2
.align 32
.endm
@@ -1261,9 +1142,7 @@
.endm
ENTRY(tl1_data_excptn_trap)
- RESUME_SPILLFILL_MMU_CLR_SFSR
- ba %xcc, tl1_sfsr_trap
- mov T_DATA_EXCEPTION | T_KERNEL, %g2
+
END(tl1_data_excptn_trap)
.macro tl1_align
@@ -1273,25 +1152,9 @@
.endm
ENTRY(tl1_align_trap)
- RESUME_SPILLFILL_ALIGN
- ba %xcc, tl1_sfsr_trap
- mov T_MEM_ADDRESS_NOT_ALIGNED | T_KERNEL, %g2
END(tl1_data_excptn_trap)
ENTRY(tl1_sfsr_trap)
- wr %g0, ASI_DMMU, %asi
- ldxa [%g0 + AA_DMMU_SFAR] %asi, %g3
- ldxa [%g0 + AA_DMMU_SFSR] %asi, %g4
- stxa %g0, [%g0 + AA_DMMU_SFSR] %asi
- membar #Sync
-
- tl1_split
- clr %o1
- set trap, %o2
- mov %g3, %o4
- mov %g4, %o5
- ba %xcc, tl1_trap
- mov %g2, %o0
END(tl1_sfsr_trap)
.macro tl1_intr level, mask
@@ -1869,52 +1732,52 @@
tl0_gen T_BREAKPOINT ! 0x76
tl0_reserved 5 ! 0x77-0x7b
tl0_cpu_mondo:
- tl0_cpu_mondo ! 0x7c
+ cpu_mondo ! 0x7c
tl0_dev_mondo:
- tl0_dev_mondo ! 0x7d
+ dev_mondo ! 0x7d
tl0_resumable_error:
- tl0_resumable_error ! 0x7e
+ resumable_error ! 0x7e
tl0_unresumable_error:
- tl0_unresumable_error ! 0x7f
+ unresumable_error ! 0x7f
tl0_spill_n_normal:
- tl0_spill_n_normal T_SPILL_0 ! 0x80
- tl0_spill_n_normal T_SPILL_1 ! 0x84
- tl0_spill_n_normal T_SPILL_2 ! 0x88
- tl0_spill_n_normal T_SPILL_3 ! 0x8c
- tl0_spill_n_normal T_SPILL_4 ! 0x90
- tl0_spill_n_normal T_SPILL_5 ! 0x94
- tl0_spill_n_normal T_SPILL_6 ! 0x98
- tl0_spill_n_normal T_SPILL_7 ! 0x9c
+ spill_n_normal T_SPILL_0 ! 0x80
+ spill_n_normal T_SPILL_1 ! 0x84
+ spill_n_normal T_SPILL_2 ! 0x88
+ spill_n_normal T_SPILL_3 ! 0x8c
+ spill_n_normal T_SPILL_4 ! 0x90
+ spill_n_normal T_SPILL_5 ! 0x94
+ spill_n_normal T_SPILL_6 ! 0x98
+ spill_n_normal T_SPILL_7 ! 0x9c
tl0_reserved 3 ! 0x9d-0x9f
tl0_spill_n_other:
- tl0_spill_n_other T_SPILL_0 ! 0xa0
- tl0_spill_n_other T_SPILL_1 ! 0xa4
- tl0_spill_n_other T_SPILL_2 ! 0xa8
- tl0_spill_n_other T_SPILL_3 ! 0xac
- tl0_spill_n_other T_SPILL_4 ! 0xb0
- tl0_spill_n_other T_SPILL_5 ! 0xb4
- tl0_spill_n_other T_SPILL_6 ! 0xb8
- tl0_spill_n_other T_SPILL_7 ! 0xbc
+ spill_n_other T_SPILL_0 ! 0xa0
+ spill_n_other T_SPILL_1 ! 0xa4
+ spill_n_other T_SPILL_2 ! 0xa8
+ spill_n_other T_SPILL_3 ! 0xac
+ spill_n_other T_SPILL_4 ! 0xb0
+ spill_n_other T_SPILL_5 ! 0xb4
+ spill_n_other T_SPILL_6 ! 0xb8
+ spill_n_other T_SPILL_7 ! 0xbc
tl0_reserved 3 ! 0xbd-0xbf
tl0_fill_n_normal:
- tl0_fill_n_normal T_FILL_0 ! 0xc0
- tl0_fill_n_normal T_FILL_1 ! 0xc4
- tl0_fill_n_normal T_FILL_2 ! 0xc8
- tl0_fill_n_normal T_FILL_3 ! 0xcc
- tl0_fill_n_normal T_FILL_4 ! 0xd0
- tl0_fill_n_normal T_FILL_5 ! 0xd4
- tl0_fill_n_normal T_FILL_6 ! 0xd8
- tl0_fill_n_normal T_FILL_7 ! 0xdc
+ fill_n_normal T_FILL_0 ! 0xc0
+ fill_n_normal T_FILL_1 ! 0xc4
+ fill_n_normal T_FILL_2 ! 0xc8
+ fill_n_normal T_FILL_3 ! 0xcc
+ fill_n_normal T_FILL_4 ! 0xd0
+ fill_n_normal T_FILL_5 ! 0xd4
+ fill_n_normal T_FILL_6 ! 0xd8
+ fill_n_normal T_FILL_7 ! 0xdc
tl0_reserved 3 ! 0xdd-0xdf
tl0_fill_n_other:
- tl0_fill_n_other T_FILL_0 ! 0xe0
- tl0_fill_n_other T_FILL_1 ! 0xe4
- tl0_fill_n_other T_FILL_2 ! 0xe8
- tl0_fill_n_other T_FILL_3 ! 0xec
- tl0_fill_n_other T_FILL_4 ! 0xf0
- tl0_fill_n_other T_FILL_5 ! 0xf4
- tl0_fill_n_other T_FILL_6 ! 0xf8
- tl0_fill_n_other T_FILL_7 ! 0xfc
+ fill_n_other T_FILL_0 ! 0xe0
+ fill_n_other T_FILL_1 ! 0xe4
+ fill_n_other T_FILL_2 ! 0xe8
+ fill_n_other T_FILL_3 ! 0xec
+ fill_n_other T_FILL_4 ! 0xf0
+ fill_n_other T_FILL_5 ! 0xf4
+ fill_n_other T_FILL_6 ! 0xf8
+ fill_n_other T_FILL_7 ! 0xfc
tl0_reserved 3 ! 0xfd-0xff
tl0_soft:
tl0_gen T_SYSCALL ! 0x100
@@ -1950,10 +1813,8 @@
tl0_gen T_SYSCALL ! 0x142
tl0_gen T_SYSCALL ! 0x143
tl0_reserved 188 ! 0x144-0x1ff
-
-
tll_base:
- tll_reserved 8 ! 0x200-0x207
+ tl1_reserved 8 ! 0x200-0x207
tll_insn_excptn:
tl1_insn_excptn ! 0x208
tl1_reserved 7 ! 0x209-0x20f
@@ -1997,52 +1858,52 @@
tl1_gen T_BREAKPOINT ! 0x276
tl1_reserved 5 ! 02x77-0x27b
tl1_cpu_mondo:
- tl1_cpu_mondo ! 0x27c
+ cpu_mondo ! 0x27c
tl1_dev_mondo:
- tl1_dev_mondo ! 0x27d
+ dev_mondo ! 0x27d
tl1_resumable_error:
- tl1_resumable_error ! 0x27e
+ resumable_error ! 0x27e
tl1_unresumable_error:
- tl1_unresumable_error ! 0x27f
+ unresumable_error ! 0x27f
tl1_spill_n_normal:
- tl1_spill_n_normal T_SPILL_0 ! 0x280
- tl1_spill_n_normal T_SPILL_1 ! 0x284
- tl1_spill_n_normal T_SPILL_2 ! 0x288
- tl1_spill_n_normal T_SPILL_3 ! 0x28c
- tl1_spill_n_normal T_SPILL_4 ! 0x290
- tl1_spill_n_normal T_SPILL_5 ! 0x294
- tl1_spill_n_normal T_SPILL_6 ! 0x298
- tl1_spill_n_normal T_SPILL_7 ! 0x29c
+ spill_n_normal T_SPILL_0 ! 0x280
+ spill_n_normal T_SPILL_1 ! 0x284
+ spill_n_normal T_SPILL_2 ! 0x288
+ spill_n_normal T_SPILL_3 ! 0x28c
+ spill_n_normal T_SPILL_4 ! 0x290
+ spill_n_normal T_SPILL_5 ! 0x294
+ spill_n_normal T_SPILL_6 ! 0x298
+ spill_n_normal T_SPILL_7 ! 0x29c
tl1_reserved 3 ! 0x29d-0x29f
tl1_spill_n_other:
- tl1_spill_n_other T_SPILL_0 ! 0x2a0
- tl1_spill_n_other T_SPILL_1 ! 0x2a4
- tl1_spill_n_other T_SPILL_2 ! 0x2a8
- tl1_spill_n_other T_SPILL_3 ! 0x2ac
- tl1_spill_n_other T_SPILL_4 ! 0x2b0
- tl1_spill_n_other T_SPILL_5 ! 0x2b4
- tl1_spill_n_other T_SPILL_6 ! 0x2b8
- tl1_spill_n_other T_SPILL_7 ! 0x2bc
+ spill_n_other T_SPILL_0 ! 0x2a0
+ spill_n_other T_SPILL_1 ! 0x2a4
+ spill_n_other T_SPILL_2 ! 0x2a8
+ spill_n_other T_SPILL_3 ! 0x2ac
+ spill_n_other T_SPILL_4 ! 0x2b0
+ spill_n_other T_SPILL_5 ! 0x2b4
+ spill_n_other T_SPILL_6 ! 0x2b8
+ spill_n_other T_SPILL_7 ! 0x2bc
tl1_reserved 3 ! 0x2bd-0x2bf
tl1_fill_n_normal:
- tl1_fill_n_normal T_FILL_0 ! 0x2c0
- tl1_fill_n_normal T_FILL_1 ! 0x2c4
- tl1_fill_n_normal T_FILL_2 ! 0x2c8
- tl1_fill_n_normal T_FILL_3 ! 0x2cc
- tl1_fill_n_normal T_FILL_4 ! 0x2d0
- tl1_fill_n_normal T_FILL_5 ! 0x2d4
- tl1_fill_n_normal T_FILL_6 ! 0x2d8
- tl1_fill_n_normal T_FILL_7 ! 0x2dc
+ fill_n_normal T_FILL_0 ! 0x2c0
+ fill_n_normal T_FILL_1 ! 0x2c4
+ fill_n_normal T_FILL_2 ! 0x2c8
+ fill_n_normal T_FILL_3 ! 0x2cc
+ fill_n_normal T_FILL_4 ! 0x2d0
+ fill_n_normal T_FILL_5 ! 0x2d4
+ fill_n_normal T_FILL_6 ! 0x2d8
+ fill_n_normal T_FILL_7 ! 0x2dc
tl1_reserved 3 ! 0x2dd-0x2df
tl1_fill_n_other:
- tl1_fill_n_other T_FILL_0 ! 0x2e0
- tl1_fill_n_other T_FILL_1 ! 0x2e4
- tl1_fill_n_other T_FILL_2 ! 0x2e8
- tl1_fill_n_other T_FILL_3 ! 0x2ec
- tl1_fill_n_other T_FILL_4 ! 0x2f0
- tl1_fill_n_other T_FILL_5 ! 0x2f4
- tl1_fill_n_other T_FILL_6 ! 0x2f8
- tl1_fill_n_other T_FILL_7 ! 0x2fc
+ fill_n_other T_FILL_0 ! 0x2e0
+ fill_n_other T_FILL_1 ! 0x2e4
+ fill_n_other T_FILL_2 ! 0x2e8
+ fill_n_other T_FILL_3 ! 0x2ec
+ fill_n_other T_FILL_4 ! 0x2f0
+ fill_n_other T_FILL_5 ! 0x2f4
+ fill_n_other T_FILL_6 ! 0x2f8
+ fill_n_other T_FILL_7 ! 0x2fc
tl1_reserved 3 ! 0x2fd-0x2ff
tl1_soft:
tl1_reserved 256 ! 0x300-0x3ff
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/hcall.S#2 (text+ko) ====
@@ -29,7 +29,6 @@
/*
* Hypervisor calls
*/
-#define LOCORE
#define _ASM
#include <machine/asm.h>
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/interrupt.S#3 (text+ko) ====
@@ -34,124 +34,6 @@
#include "assym.s"
-/*
- * Handle a vectored interrupt.
- *
- * This is either a data bearing mondo vector interrupt, or a cross trap
- * request from another cpu. In either case the hardware supplies an
- * interrupt packet, in the form of 3 data words which are read from internal
- * registers. A data bearing mondo vector packet consists of an interrupt
- * number in the first data word, and zero in 2nd and 3rd. We use the
- * interrupt number to find the function, argument and priority from the
- * intr_vector table, allocate and fill in an intr_request from the per-cpu
- * free list, link it onto the per-cpu active list and finally post a softint
- * at the desired priority. Cross trap requests come in 2 forms, direct
- * and queued. Direct requests are distinguished by the first data word
- * being zero. The 2nd data word carries a function to call and the 3rd
- * an argument to pass. The function is jumped to directly. It executes
- * in nucleus context on interrupt globals and with all interrupts disabled,
- * therefore it must be fast, and the things that it can do are limited.
- * Queued cross trap requests are handled much like mondo vectors, except
- * that the function, argument and priority are contained in the interrupt
- * packet itself. They are distinguished by the upper 4 bits of the data
- * word being non-zero, which specifies the priority of the softint to
- * deliver.
- *
- * Register usage:
- * %g1 - pointer to intr_request
- * %g2 - pointer to intr_vector, temp once required data is loaded
- * %g3 - interrupt number for mondo vectors, unused otherwise
- * %g4 - function, from the interrupt packet for cross traps, or
- * loaded from the interrupt registers for mondo vecors
- * %g5 - argument, as above for %g4
- * %g6 - softint priority
- */
-ENTRY(intr_vector)
- /*
- * Load the interrupt packet from the hardware.
- */
- wr %g0, ASI_SDB_INTR_R, %asi
- ldxa [%g0 + AA_SDB_INTR_D0] %asi, %g3
- ldxa [%g0 + AA_SDB_INTR_D1] %asi, %g4
- ldxa [%g0 + AA_SDB_INTR_D2] %asi, %g5
-#ifdef notyet
- /* XXX SUN4V_FIXME */
- stxa %g0, [%g0] ASI_INTR_RECEIVE
-#endif
- membar #Sync
-
- /*
- * If the first data word is zero this is a direct cross trap request.
- * The 2nd word points to code to execute and the 3rd is an argument
- * to pass. Jump to it.
- */
- brnz,a,pt %g3, 1f
- nop
- jmpl %g4, %g0
- nop
- /* NOTREACHED */
-
- /*
- * If the high 4 bits of the 1st data word are non-zero, this is a
- * queued cross trap request to be delivered as a softint. The high
- * 4 bits of the 1st data word specify a priority, and the 2nd and
- * 3rd a function and argument.
- */
-1: srlx %g3, 60, %g6
- brnz,a,pn %g6, 2f
- clr %g3
-
- /*
- * Find the function, argument and desired priority from the
- * intr_vector table.
- */
- SET(intr_vectors, %g4, %g2)
- sllx %g3, IV_SHIFT, %g4
- add %g2, %g4, %g2
-
- ldx [%g2 + IV_FUNC], %g4
- ldx [%g2 + IV_ARG], %g5
- lduw [%g2 + IV_PRI], %g6
-
- /*
- * Get an intr_request from the free list. There should always be one
- * unless we are getting an interrupt storm from stray interrupts, in
- * which case the we will deference a NULL pointer and panic.
- */
-2: ldx [PCPU(IRFREE)], %g1
- ldx [%g1 + IR_NEXT], %g2
- stx %g2, [PCPU(IRFREE)]
-
- /*
- * Store the vector number, function, argument and priority.
- */
- stw %g3, [%g1 + IR_VEC]
- stx %g4, [%g1 + IR_FUNC]
- stx %g5, [%g1 + IR_ARG]
- stw %g6, [%g1 + IR_PRI]
-
- /*
- * Link it onto the end of the active list.
- */
- stx %g0, [%g1 + IR_NEXT]
- ldx [PCPU(IRTAIL)], %g4
- stx %g1, [%g4]
- add %g1, IR_NEXT, %g1
- stx %g1, [PCPU(IRTAIL)]
-
- /*
- * Trigger a softint at the level indicated by the priority.
- */
- mov 1, %g1
- sllx %g1, %g6, %g1
- wr %g1, 0, %set_softint
-
- /*
- * Done, retry the instruction.
- */
- retry
-END(intr_vector)
-
ENTRY(intr_fast)
save %sp, -CCFSZ, %sp
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/machdep.c#4 (text+ko) ====
@@ -340,8 +340,6 @@
end = (vm_offset_t)_end;
}
- cache_init(child);
-
cpu_block_copy = bcopy;
cpu_block_zero = bzero;
@@ -666,7 +664,10 @@
#ifdef SMP
cpu_mp_shutdown();
#endif
+#ifdef notyet
+/* XXX SUN4V_FIXME */
openfirmware_exit(args);
+#endif
}
/* Get current clock frequency for the given cpu id. */
==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/pmap.c#3 (text+ko) ====
@@ -54,9 +54,22 @@
#define PMAP_SHPGPERPROC 200
#endif
+cache_enable_t *cache_enable;
+cache_flush_t *cache_flush;
+dcache_page_inval_t *dcache_page_inval;
+icache_page_inval_t *icache_page_inval;
+
+/*
+ * Virtual and physical address of message buffer.
+ */
+struct msgbuf *msgbufp;
+vm_paddr_t msgbuf_phys;
+
+
/*
* Map of physical memory reagions.
*/
+vm_paddr_t phys_avail[128];
static struct ofw_mem_region mra[128];
static struct ofw_map translations[128];
static int translations_size;
@@ -70,19 +83,30 @@
static vm_offset_t pmap_temp_map_1;
static vm_offset_t pmap_temp_map_2;
+
/*
+ * First and last available kernel virtual addresses.
+ */
+vm_offset_t virtual_avail;
+vm_offset_t virtual_end;
+vm_offset_t kernel_vm_end;
+
+vm_offset_t vm_max_kernel_address;
+struct tte *tsb_kernel;
+vm_size_t tsb_kernel_mask;
+vm_size_t tsb_kernel_size;
+vm_paddr_t tsb_kernel_phys;
+
+/*
+ * Kernel pmap.
+ */
+struct pmap kernel_pmap_store;
+
+/*
* Allocate physical memory for use in pmap_bootstrap.
*/
static vm_paddr_t pmap_bootstrap_alloc(vm_size_t size);
-extern int tl1_immu_miss_patch_1[];
-extern int tl1_immu_miss_patch_2[];
-extern int tl1_dmmu_miss_patch_1[];
-extern int tl1_dmmu_miss_patch_2[];
-extern int tl1_dmmu_prot_patch_1[];
-extern int tl1_dmmu_prot_patch_2[];
-
>>> TRUNCATED FOR MAIL (1000 lines) <<<
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