PERFORCE change 111413 for review
Sam Leffler
sam at FreeBSD.org
Sun Dec 10 15:16:53 PST 2006
http://perforce.freebsd.org/chv.cgi?CH=111413
Change 111413 by sam at sam_ebb on 2006/12/10 23:15:30
import patch 3 from mcr
Affected files ...
.. //depot/projects/crypto/sys/dev/hifn/hifn7751.c#3 edit
.. //depot/projects/crypto/sys/dev/hifn/hifn7751reg.h#2 edit
.. //depot/projects/crypto/sys/dev/hifn/hifn7751var.h#2 edit
Differences ...
==== //depot/projects/crypto/sys/dev/hifn/hifn7751.c#3 (text+ko) ====
@@ -49,6 +49,7 @@
#include "opt_hifn.h"
#include <sys/param.h>
+#include <sys/conf.h>
#include <sys/systm.h>
#include <sys/proc.h>
#include <sys/errno.h>
@@ -60,6 +61,8 @@
#include <sys/mutex.h>
#include <sys/sysctl.h>
+#include <sys/uio.h>
+
#include <vm/vm.h>
#include <vm/pmap.h>
@@ -92,6 +95,7 @@
static int hifn_suspend(device_t);
static int hifn_resume(device_t);
static void hifn_shutdown(device_t);
+static struct cdevsw vulcanpk_cdevsw; /* forward declaration */
static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *);
static int hifn_freesession(device_t, u_int64_t);
@@ -166,7 +170,11 @@
sc->sc_bar0_lastreg = (bus_size_t) -1;
return (v);
}
+#ifdef HIFN_DEBUG
+#define WRITE_REG_0(sc, reg, val) ( device_printf(sc->sc_dev, "write-0 %04x %08x\n", reg, val), hifn_write_reg_0(sc, reg, val))
+#else
#define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val)
+#endif
static __inline u_int32_t
READ_REG_1(struct hifn_softc *sc, bus_size_t reg)
@@ -175,7 +183,11 @@
sc->sc_bar1_lastreg = (bus_size_t) -1;
return (v);
}
+#ifdef HIFN_DEBUG
+#define WRITE_REG_1(sc, reg, val) ( device_printf(sc->sc_dev, "write-1 %04x %08x\n", reg, val), hifn_write_reg_1(sc, reg, val))
+#else
#define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val)
+#endif
SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters");
@@ -288,6 +300,20 @@
* always will allow the card to work. If a card is using the PCI
* bus clock and in a 33MHz slot then it will be operating at half
* speed until the correct information is provided.
+ *
+ * According Mike Ham of HiFn, almost every board in existence has
+ * an external crystal populated at 66Mhz. Using PCI can be a problem
+ * on modern motherboards, because PCI33 can have clocks from 0 to 33Mhz,
+ * and some have non-PCI-compliant spread-spectrum clocks, which can confuse
+ * the pll.
+ *
+ * On Linux, there is no way to set pllconfig except on the boot
+ * command line for static kernels. Even though the string can get adjusted
+ * afterwards, the device will not be reconfigured.
+ *
+ * On FreeBSD, you can edit the device hints by editing /boot/device.hints,
+ * and this too, is loaded only at boot time. See device.hints(5).
+ *
*/
static void
hifn_getpllconfig(device_t dev, u_int *pll)
@@ -299,7 +325,7 @@
if (resource_string_value("hifn", device_get_unit(dev),
"pllconfig", &pllspec))
- pllspec = "pci66";
+ pllspec = "ext66";
fl = 33, fh = 66;
pllconfig = 0;
if (strncmp(pllspec, "ext", 3) == 0) {
@@ -435,6 +461,11 @@
sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res);
sc->sc_bar1_lastreg = (bus_size_t) -1;
+#if 0
+ sc->sc_bar1fake = malloc(4096, M_DEVBUF, M_NOWAIT);
+ memset(sc->sc_bar1fake, 'X', 4096);
+#endif
+
hifn_set_retry(sc);
/*
@@ -561,11 +592,16 @@
device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram",
hifn_partname(sc), rev,
rseg, rbase, sc->sc_drammodel ? 'd' : 's');
- if (sc->sc_flags & HIFN_IS_7956)
+ if (sc->sc_flags & HIFN_IS_7956) {
+#if 0
printf(", pll=0x%x<%s clk, %ux mult>",
sc->sc_pllconfig,
sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci",
2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11));
+#else
+ printf(", pll=defaulting");
+#endif
+ }
printf("\n");
sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
@@ -781,6 +817,7 @@
sc->sc_rnghz = hz / 100;
else
sc->sc_rnghz = 1;
+ device_printf(sc->sc_dev, "enabling entropy gathering\n");
callout_init(&sc->sc_rngto, CALLOUT_MPSAFE);
callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
}
@@ -790,6 +827,11 @@
WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
sc->sc_dmaier |= HIFN_DMAIER_PUBDONE;
WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
+
+ sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0,
+ UID_ROOT, GID_WHEEL, 0666,
+ "vulcanpk");
+ sc->sc_pkdev->si_drv1 = sc;
}
return (0);
@@ -804,6 +846,7 @@
int i;
if (sc->sc_flags & HIFN_IS_7811) {
+ /* ONLY VALID ON 7811!!!! */
for (i = 0; i < 5; i++) {
sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS);
if (sts & HIFN_7811_RNGSTS_UFL) {
@@ -846,10 +889,15 @@
hifn_puc_wait(struct hifn_softc *sc)
{
int i;
+ int reg = HIFN_0_PUCTRL;
+
+ if (sc->sc_flags & HIFN_IS_7956) {
+ reg = HIFN_0_PUCTRL2;
+ }
for (i = 5000; i > 0; i--) {
DELAY(1);
- if (!(READ_REG_0(sc, HIFN_0_PUCTRL) & HIFN_PUCTRL_RESET))
+ if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET))
break;
}
if (!i)
@@ -863,7 +911,13 @@
hifn_reset_puc(struct hifn_softc *sc)
{
/* Reset processing unit */
- WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
+ int reg = HIFN_0_PUCTRL;
+
+ if (sc->sc_flags & HIFN_IS_7956) {
+ reg = HIFN_0_PUCTRL2;
+ }
+ WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA);
+
hifn_puc_wait(sc);
}
@@ -932,7 +986,16 @@
}
if (reg == 1000)
printf(": cram init timeout\n");
+ } else {
+ /* set up DMA configuration register #2 */
+ /* turn off all PK and BAR0 swaps */
+ WRITE_REG_1(sc, HIFN_1_DMA_CNFG2,
+ (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)|
+ (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)|
+ (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)|
+ (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT));
}
+
}
static u_int32_t
@@ -1170,13 +1233,15 @@
/* turn off the clocks and insure bypass is set */
pll = READ_REG_1(sc, HIFN_1_PLL);
pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL))
- | HIFN_PLL_BP;
+ | HIFN_PLL_BP | HIFN_PLL_MBSET;
WRITE_REG_1(sc, HIFN_1_PLL, pll);
DELAY(10*1000); /* 10ms */
+
/* change configuration */
pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig;
WRITE_REG_1(sc, HIFN_1_PLL, pll);
DELAY(10*1000); /* 10ms */
+
/* disable bypass */
pll &= ~HIFN_PLL_BP;
WRITE_REG_1(sc, HIFN_1_PLL, pll);
@@ -2858,3 +2923,46 @@
}
bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);
}
+
+
+/*
+ * this code provides support for mapping the PK engine's register
+ * into a userspace program.
+ *
+ */
+static int
+vulcanpk_mmap(struct cdev *dev, vm_offset_t offset,
+ vm_paddr_t *paddr, int nprot)
+{
+ struct hifn_softc *sc;
+ vm_paddr_t pd;
+ void *b;
+
+ sc = dev->si_drv1;
+
+#if 0
+ b = sc->sc_bar1fake;
+ pd = vtophys(b);
+#else
+ pd = rman_get_start(sc->sc_bar1res);
+ b = rman_get_virtual(sc->sc_bar1res);
+#endif
+
+#if 0
+ printf("vpk mmap: %p(%08x) offset=%d\n", b, pd, offset);
+ hexdump(b, HIFN_1_PUB_MEMEND, "vpk", 0);
+#endif
+
+ if (offset == 0) {
+ *paddr = pd;
+ return (0);
+ }
+ return (-1);
+}
+
+static struct cdevsw vulcanpk_cdevsw = {
+ .d_version = D_VERSION,
+ .d_mmap = vulcanpk_mmap,
+ .d_name = "vulcanpk",
+};
+
==== //depot/projects/crypto/sys/dev/hifn/hifn7751reg.h#2 (text+ko) ====
@@ -118,7 +118,10 @@
#define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
#define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
#define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
-#define HIFN_0_SPACESIZE 0x20 /* Register space size */
+#define HIFN_0_PUCTRL2 0x28 /* Processing Unit Control -- second mapping */
+#define HIFN_0_MUTE1 0x80
+#define HIFN_0_MUTE2 0x90
+#define HIFN_0_SPACESIZE 0x100 /* Register space size */
/* Processing Unit Control Register (HIFN_0_PUCTRL) */
#define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
@@ -200,7 +203,7 @@
#define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
/* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
-#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */
+#define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as this value */
/*
* DMA Interface Registers (offset from BASEREG1)
@@ -217,17 +220,21 @@
#define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
#define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
#define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */
+#define HIFN_1_DMA_CNFG2 0x6c /* 7955/7956: dma config #2 */
#define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
#define HIFN_1_REVID 0x98 /* Revision ID */
#define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */
#define HIFN_1_PUB_BASE 0x300 /* Public Base Address */
-#define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */
-#define HIFN_1_PUB_OP 0x308 /* Public Operand */
-#define HIFN_1_PUB_STATUS 0x30c /* Public Status */
-#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt nable */
+#define HIFN_1_PUB_OPLEN 0x304 /* 7951-compat Public Operand Length */
+#define HIFN_1_PUB_OP 0x308 /* 7951-compat Public Operand */
+#define HIFN_1_PUB_STATUS 0x30c /* 7951-compat Public Status */
+#define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */
#define HIFN_1_RNG_CONFIG 0x314 /* RNG config */
#define HIFN_1_RNG_DATA 0x318 /* RNG data */
+#define HIFN_1_PUB_MODE 0x320 /* PK mode */
+#define HIFN_1_PUB_FIFO_OPLEN 0x380 /* first element of oplen fifo */
+#define HIFN_1_PUB_FIFO_OP 0x384 /* first element of op fifo */
#define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */
#define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */
@@ -305,6 +312,16 @@
#define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
#define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
+/* DMA Configuration Register (HIFN_1_DMA_CNFG2) */
+#define HIFN_DMACNFG2_PKSWAP32 (1 << 19) /* swap the OPLEN/OP reg */
+#define HIFN_DMACNFG2_PKSWAP8 (1 << 18) /* swap the bits of OPLEN/OP */
+#define HIFN_DMACNFG2_BAR0_SWAP32 (1<<17) /* swap the bytes of BAR0 */
+#define HIFN_DMACNFG2_BAR1_SWAP8 (1<<16) /* swap the bits of BAR0 */
+#define HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT 12
+#define HIFN_DMACNFG2_INIT_READ_BURST_SHIFT 8
+#define HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT 4
+#define HIFN_DMACNFG2_TGT_READ_BURST_SHIFT 0
+
/* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */
#define HIFN_7811_RNGENA_ENA 0x00000001 /* enable RNG */
@@ -358,6 +375,11 @@
/* Public status register (HIFN_1_PUB_STATUS) */
#define HIFN_PUBSTS_DONE 0x00000001 /* operation done */
#define HIFN_PUBSTS_CARRY 0x00000002 /* carry */
+#define HIFN_PUBSTS_FIFO_EMPTY 0x00000100 /* fifo empty */
+#define HIFN_PUBSTS_FIFO_FULL 0x00000200 /* fifo full */
+#define HIFN_PUBSTS_FIFO_OVFL 0x00000400 /* fifo overflow */
+#define HIFN_PUBSTS_FIFO_WRITE 0x000f0000 /* fifo write */
+#define HIFN_PUBSTS_FIFO_READ 0x0f000000 /* fifo read */
/* Public interrupt enable register (HIFN_1_PUB_IEN) */
#define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */
@@ -407,6 +429,13 @@
*/
#define HIFN_PLL_CONFIG (HIFN_PLL_IS|HIFN_PLL_ND|HIFN_PLL_REF_SEL)
+/*
+ * Public Key Engine Mode Register
+ */
+#define HIFN_PKMODE_HOSTINVERT (1 << 0) /* HOST INVERT */
+#define HIFN_PKMODE_ENHANCED (1 << 1) /* Enable enhanced mode */
+
+
/*********************************************************************
* Structs for board commands
*
==== //depot/projects/crypto/sys/dev/hifn/hifn7751var.h#2 (text+ko) ====
@@ -183,6 +183,10 @@
int sc_needwakeup; /* ops q'd wating on resources */
int sc_curbatch; /* # ops submitted w/o int */
int sc_suspended;
+ struct cdev *sc_pkdev;
+
+ void *sc_bar1fake;
+
};
#define HIFN_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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