PERFORCE change 111152 for review

[Oleksandr Tymoshenko]

http://perforce.freebsd.org/chv.cgi?CH=111152

Change 111152 by gonzo at gonzo_hq on 2006/12/05 18:20:27

	o Stick on the moment with _jmp_buf as an array of 12 registers, 
	    do not consider signal context, let's put signals aside for a while.

Affected files ...

.. //depot/projects/mips2/src/lib/libc/mips/gen/_setjmp.S#3 edit

Differences ...

==== //depot/projects/mips2/src/lib/libc/mips/gen/_setjmp.S#3 (text+ko) ====

@@ -67,19 +67,19 @@
 #endif
 
 	.set push
-	li	v0, 0xACEDBADE			# sigcontext magic number
-	sw	ra, (2 * 4)(a0)			# sc_pc = return address
-	sw	v0, (_OFFSETOF_SC_REGS)(a0)	#   saved in sc_regs[0]
-	sw	s0, (S0 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	sw	s1, (S1 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	sw	s2, (S2 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	sw	s3, (S3 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	sw	s4, (S4 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	sw	s5, (S5 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	sw	s6, (S6 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	sw	s7, (S7 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	sw	sp, (SP * SZREG + _OFFSETOF_SC_REGS)(a0)
-	sw	s8, (S8 * SZREG + _OFFSETOF_SC_REGS)(a0)
+	li	v0, 0xACEDBADE
+	sw	v0, (a0)
+	sw	ra, (1  * SZREG)(a0)
+	sw	s0, (2  * SZREG)(a0)
+	sw	s1, (3  * SZREG)(a0)
+	sw	s2, (4  * SZREG)(a0)
+	sw	s3, (5  * SZREG)(a0)
+	sw	s4, (6  * SZREG)(a0)
+	sw	s5, (7  * SZREG)(a0)
+	sw	s6, (8  * SZREG)(a0)
+	sw	s7, (9  * SZREG)(a0)
+	sw	sp, (10 * SZREG)(a0)
+	sw	s8, (11 * SZREG)(a0)
 #ifndef SOFTFLOAT
 	cfc1	v0, $31				# too bad cant check if FP used
 	swc1	$f20, (20 * 4 + _OFFSETOF_SC_FPREGS)(a0)
@@ -111,23 +111,23 @@
 	.set    noreorder
 #endif  
 	.set push
-	lw	v0, (_OFFSETOF_SC_REGS)(a0)	# get magic number
-	lw	ra, (2 * 4)(a0)
+	lw	v0, (a0)	# get magic number
+	lw	ra, (1  * SZREG)(a0)
 	li	t0, 0xACEDBADE
 	bne	v0, t0, botch		# jump if error
 	addu	sp, sp, 32			# does not matter, sanity
-	lw	s0, (S0 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	lw	s1, (S1 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	lw	s2, (S2 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	lw	s3, (S3 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	lw	s4, (S4 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	lw	s5, (S5 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	lw	s6, (S6 * SZREG + _OFFSETOF_SC_REGS)(a0)
-	lw	s7, (S7 * SZREG + _OFFSETOF_SC_REGS)(a0)
+	lw	s0, (2  * SZREG)(a0)
+	lw	s1, (3  * SZREG)(a0)
+	lw	s2, (4  * SZREG)(a0)
+	lw	s3, (5  * SZREG)(a0)
+	lw	s4, (6  * SZREG)(a0)
+	lw	s5, (7  * SZREG)(a0)
+	lw	s6, (8  * SZREG)(a0)
+	lw	s7, (9  * SZREG)(a0)
+	lw	sp, (10 * SZREG)(a0)
+	lw	s8, (11 * SZREG)(a0)
+#ifndef SOFTFLOAT
 	lw	v0, (32 * 4 + _OFFSETOF_SC_FPREGS)(a0)	# get fpu status
-	lw	sp, (SP * SZREG + _OFFSETOF_SC_REGS)(a0)
-	lw	s8, (S8 * SZREG + _OFFSETOF_SC_REGS)(a0)
-#ifndef SOFTFLOAT
 	ctc1	v0, $31
 	lwc1	$f20, (20 * 4 + _OFFSETOF_SC_FPREGS)(a0)
 	lwc1	$f21, (21 * 4 + _OFFSETOF_SC_FPREGS)(a0)