PERFORCE change 94907 for review
Robert Watson
rwatson at FreeBSD.org
Mon Apr 10 08:14:00 UTC 2006
http://perforce.freebsd.org/chv.cgi?CH=94907
Change 94907 by rwatson at rwatson_sesame on 2006/04/10 08:12:57
Integrate trustedbsd_acl_nfsv4.
Affected files ...
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/amd64/amd64/io_apic.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/arm/cpufunc.c#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/arm/swtch.S#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/arm/trap.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/arm/undefined.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/at91/at91.c#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/at91/at91_twi.c#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/at91/at91_usartreg.h#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/at91/if_ate.c#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/at91/uart_dev_at91usart.c#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/include/pmap.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/sa11x0/uart_dev_sa1110.c#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/xscale/i80321/i80321_timer.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/conf/options.arm#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/aac/aac.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/acpi_support/acpi_asus.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/amr/amr.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/amr/amr_pci.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/amr/amrvar.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/drm-preprocess.sh#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/drm.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/drm_agpsupport.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/drm_pciids.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/i915_dma.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/i915_drm.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/i915_drv.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/i915_irq.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/i915_mem.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/mga_drv.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/r300_cmdbuf.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/r300_reg.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/radeon_cp.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/radeon_drm.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/radeon_drv.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/radeon_state.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/savage_bci.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/savage_state.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/sis_ds.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/sis_ds.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/drm/sis_mm.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/em/LICENSE#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/em/README#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/em/if_em.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/em/if_em_hw.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/em/if_em_hw.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/dev/mfi/mfi.c#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/geom/eli/g_eli.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/geom/geom.h#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/geom/geom_bsd.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/geom/geom_ccd.c#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/geom/geom_ctl.c#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/geom/geom_disk.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/geom/geom_gpt.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/geom/geom_slice.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/geom/geom_subr.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/i386/i386/io_apic.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/i386/i386/machdep.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/i386/isa/npx.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/kern/kern_event.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/kern/subr_witness.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/kern/uipc_proto.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/net/raw_usrreq.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/netgraph/ng_socket.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/netinet/tcp_input.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/netinet/tcp_sack.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/netinet6/udp6_usrreq.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/netipsec/ipsec.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/netipsec/ipsec.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/netipsec/xform_ah.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/netipsec/xform_esp.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/netnatm/natm.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/nfsclient/nfs_bio.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/nfsclient/nfs_vnops.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/nfsclient/nfsnode.h#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/nfsserver/nfs_srvsock.c#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/posix4/ksched.c#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/posix4/p1003_1b.c#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/powerpc/conf/GENERIC#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/security/mac/mac_vfs.c#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/sys/filedesc.h#2 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/sys/mac.h#3 integrate
.. //depot/projects/trustedbsd/acl_nfsv4/src/sys/sys/mac_policy.h#3 integrate
Differences ...
==== //depot/projects/trustedbsd/acl_nfsv4/src/sys/amd64/amd64/io_apic.c#3 (text+ko) ====
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/amd64/amd64/io_apic.c,v 1.23 2006/03/20 19:39:07 jhb Exp $");
+__FBSDID("$FreeBSD: src/sys/amd64/amd64/io_apic.c,v 1.24 2006/04/05 20:43:19 jhb Exp $");
#include "opt_atpic.h"
#include "opt_isa.h"
@@ -89,6 +89,7 @@
u_int io_edgetrigger:1;
u_int io_masked:1;
int io_bus:4;
+ uint32_t io_lowreg;
};
struct ioapic {
@@ -207,9 +208,7 @@
mtx_lock_spin(&icu_lock);
if (intpin->io_masked) {
- flags = ioapic_read(io->io_addr,
- IOAPIC_REDTBL_LO(intpin->io_intpin));
- flags &= ~(IOART_INTMASK);
+ flags = intpin->io_lowreg & ~IOART_INTMASK;
ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
flags);
intpin->io_masked = 0;
@@ -226,9 +225,7 @@
mtx_lock_spin(&icu_lock);
if (!intpin->io_masked && !intpin->io_edgetrigger) {
- flags = ioapic_read(io->io_addr,
- IOAPIC_REDTBL_LO(intpin->io_intpin));
- flags |= IOART_INTMSET;
+ flags = intpin->io_lowreg | IOART_INTMSET;
ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
flags);
intpin->io_masked = 1;
@@ -313,6 +310,7 @@
/* Write the values to the APIC. */
mtx_lock_spin(&icu_lock);
+ intpin->io_lowreg = low;
ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin));
value &= ~IOART_DEST;
==== //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/arm/cpufunc.c#2 (text+ko) ====
@@ -45,7 +45,7 @@
* Created : 30/01/97
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/arm/arm/cpufunc.c,v 1.9 2005/05/25 13:46:32 cognet Exp $");
+__FBSDID("$FreeBSD: src/sys/arm/arm/cpufunc.c,v 1.10 2006/04/09 23:07:31 cognet Exp $");
#include <sys/cdefs.h>
@@ -1530,7 +1530,8 @@
cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
- | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE;
+ | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE |
+ CPU_CONTROL_ROUNDROBIN;
cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
| CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
| CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
==== //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/arm/swtch.S#3 (text+ko) ====
@@ -83,7 +83,7 @@
#include <machine/asm.h>
#include <machine/asmacros.h>
#include <machine/armreg.h>
-__FBSDID("$FreeBSD: src/sys/arm/arm/swtch.S,v 1.18 2005/10/04 20:47:27 cognet Exp $");
+__FBSDID("$FreeBSD: src/sys/arm/arm/swtch.S,v 1.19 2006/04/09 20:16:47 cognet Exp $");
/*
@@ -467,7 +467,7 @@
bl _C_LABEL(fork_exit)
/* Kill irq"s */
mrs r0, cpsr
- orr r0, r0, #(I32_bit)
+ orr r0, r0, #(I32_bit|F32_bit)
msr cpsr_c, r0
DO_AST
PULLFRAME
==== //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/arm/trap.c#3 (text+ko) ====
@@ -82,7 +82,7 @@
#include "opt_ktrace.h"
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/arm/arm/trap.c,v 1.23 2006/03/01 20:43:51 cognet Exp $");
+__FBSDID("$FreeBSD: src/sys/arm/arm/trap.c,v 1.24 2006/04/09 20:16:47 cognet Exp $");
#include <sys/types.h>
@@ -271,9 +271,13 @@
/* Grab the current pcb */
pcb = td->td_pcb;
/* Re-enable interrupts if they were enabled previously */
- if (td->td_md.md_spinlock_count == 0 &&
- __predict_true(tf->tf_spsr & I32_bit) == 0)
- enable_interrupts(I32_bit);
+ if (td->td_md.md_spinlock_count == 0) {
+ if (__predict_true(tf->tf_spsr & I32_bit) == 0)
+ enable_interrupts(I32_bit);
+ if (__predict_true(tf->tf_spsr & F32_bit) == 0)
+ enable_interrupts(F32_bit);
+ }
+
/* Invoke the appropriate handler, if necessary */
if (__predict_false(data_aborts[fsr & FAULT_TYPE_MASK].func != NULL)) {
@@ -487,6 +491,7 @@
mode = TRAP_USERMODE(tf) ? "user" : "kernel";
+ disable_interrupts(I32_bit|F32_bit);
if (td != NULL) {
printf("Fatal %s mode data abort: '%s'\n", mode,
data_aborts[fsr & FAULT_TYPE_MASK].desc);
@@ -730,9 +735,13 @@
thread_user_enter(td);
}
fault_pc = tf->tf_pc;
- if (td->td_md.md_spinlock_count == 0 &&
- __predict_true((tf->tf_spsr & I32_bit) == 0))
- enable_interrupts(I32_bit);
+ if (td->td_md.md_spinlock_count == 0) {
+ if (__predict_true(tf->tf_spsr & I32_bit) == 0)
+ enable_interrupts(I32_bit);
+ if (__predict_true(tf->tf_spsr & F32_bit) == 0)
+ enable_interrupts(F32_bit);
+ }
+
/* See if the cpu state needs to be fixed up */
@@ -1012,9 +1021,13 @@
* Since all syscalls *should* come from user mode it will always
* be safe to enable them, but check anyway.
*/
- if (td->td_md.md_spinlock_count == 0 && !(frame->tf_spsr & I32_bit))
- enable_interrupts(I32_bit);
-
+ if (td->td_md.md_spinlock_count == 0) {
+ if (__predict_true(frame->tf_spsr & I32_bit) == 0)
+ enable_interrupts(I32_bit);
+ if (__predict_true(frame->tf_spsr & F32_bit) == 0)
+ enable_interrupts(F32_bit);
+ }
+
syscall(td, frame, insn);
}
==== //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/arm/undefined.c#3 (text+ko) ====
@@ -48,7 +48,7 @@
#include "opt_ddb.h"
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/arm/arm/undefined.c,v 1.12 2006/03/01 18:33:45 cognet Exp $");
+__FBSDID("$FreeBSD: src/sys/arm/arm/undefined.c,v 1.13 2006/04/09 20:16:47 cognet Exp $");
#include <sys/param.h>
#include <sys/malloc.h>
@@ -189,7 +189,7 @@
/* Enable interrupts if they were enabled before the exception. */
if (!(frame->tf_spsr & I32_bit))
- enable_interrupts(I32_bit);
+ enable_interrupts(I32_bit|F32_bit);
frame->tf_pc -= INSN_SIZE;
PCPU_LAZY_INC(cnt.v_trap);
==== //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/at91/at91.c#2 (text) ====
@@ -23,7 +23,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/arm/at91/at91.c,v 1.3 2006/03/18 01:35:49 imp Exp $");
+__FBSDID("$FreeBSD: src/sys/arm/at91/at91.c,v 1.4 2006/04/06 04:32:29 imp Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -201,11 +201,14 @@
struct at91_ivar *ivar;
kid = device_add_child_ordered(dev, prio, name, unit);
- if (kid == NULL)
- return;
+ if (kid == NULL) {
+ printf("Can't add child %s%d ordered\n", name, unit);
+ return;
+ }
ivar = malloc(sizeof(*ivar), M_DEVBUF, M_WAITOK | M_ZERO);
if (ivar == NULL) {
device_delete_child(dev, kid);
+ printf("Can't add alloc ivar\n");
return;
}
device_set_ivars(kid, ivar);
==== //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/at91/at91_twi.c#2 (text) ====
@@ -23,7 +23,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/arm/at91/at91_twi.c,v 1.1 2006/02/04 23:32:13 imp Exp $");
+__FBSDID("$FreeBSD: src/sys/arm/at91/at91_twi.c,v 1.2 2006/04/06 04:31:19 imp Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -40,7 +40,10 @@
#include <arm/at91/at91rm92reg.h>
#include <arm/at91/at91_twireg.h>
-#include <arm/at91/at91_twiio.h>
+
+#include <dev/iicbus/iiconf.h>
+#include <dev/iicbus/iicbus.h>
+#include "iicbus_if.h"
struct at91_twi_softc
{
@@ -50,13 +53,12 @@
struct resource *mem_res; /* Memory resource */
struct mtx sc_mtx; /* basically a perimeter lock */
int flags;
-#define XFER_PENDING 1 /* true when transfer taking place */
-#define OPENED 2 /* Device opened */
#define RXRDY 4
-#define TXCOMP 8
#define TXRDY 0x10
- struct cdev *cdev;
uint32_t cwgr;
+ int sc_started;
+ int twi_addr;
+ device_t iicbus;
};
static inline uint32_t
@@ -79,7 +81,6 @@
#define AT91_TWI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
#define AT91_TWI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
#define AT91_TWI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
-#define CDEV2SOFTC(dev) ((dev)->si_drv1)
#define TWI_DEF_CLK 100000
static devclass_t at91_twi_devclass;
@@ -95,19 +96,6 @@
static int at91_twi_activate(device_t dev);
static void at91_twi_deactivate(device_t dev);
-/* cdev routines */
-static d_open_t at91_twi_open;
-static d_close_t at91_twi_close;
-static d_ioctl_t at91_twi_ioctl;
-
-static struct cdevsw at91_twi_cdevsw =
-{
- .d_version = D_VERSION,
- .d_open = at91_twi_open,
- .d_close = at91_twi_close,
- .d_ioctl = at91_twi_ioctl
-};
-
static int
at91_twi_probe(device_t dev)
{
@@ -137,20 +125,23 @@
AT91_TWI_LOCK_DESTROY(sc);
goto out;
}
- sc->cdev = make_dev(&at91_twi_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600,
- "twi%d", device_get_unit(dev));
- if (sc->cdev == NULL) {
- err = ENOMEM;
- goto out;
- }
- sc->cdev->si_drv1 = sc;
- sc->cwgr = TWI_CWGR_CKDIV(1) |
+ sc->cwgr = TWI_CWGR_CKDIV(8 * AT91C_MASTER_CLOCK / 90000) |
TWI_CWGR_CHDIV(TWI_CWGR_DIV(TWI_DEF_CLK)) |
TWI_CWGR_CLDIV(TWI_CWGR_DIV(TWI_DEF_CLK));
WR4(sc, TWI_CR, TWI_CR_SWRST);
WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
WR4(sc, TWI_CWGR, sc->cwgr);
+
+ WR4(sc, TWI_IER, TWI_SR_RXRDY | TWI_SR_OVRE | TWI_SR_UNRE |
+ TWI_SR_NACK);
+
+ if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL)
+ device_printf(dev, "could not allocate iicbus instance\n");
+
+ /* probe and attach the iicbus */
+ bus_generic_attach(dev);
+
out:;
if (err)
at91_twi_deactivate(dev);
@@ -160,7 +151,15 @@
static int
at91_twi_detach(device_t dev)
{
- return (EBUSY); /* XXX */
+ struct at91_twi_softc *sc;
+ int rv;
+
+ sc = device_get_softc(dev);
+ at91_twi_deactivate(dev);
+ if (sc->iicbus && (rv = device_delete_child(dev, sc->iicbus)) != 0)
+ return (rv);
+
+ return (0);
}
static int
@@ -215,13 +214,12 @@
/* Reading the status also clears the interrupt */
status = RD4(sc, TWI_SR);
+ printf("status %x\n", status);
if (status == 0)
return;
AT91_TWI_LOCK(sc);
if (status & TWI_SR_RXRDY)
sc->flags |= RXRDY;
- if (status & TWI_SR_TXCOMP)
- sc->flags |= TXCOMP;
if (status & TWI_SR_TXRDY)
sc->flags |= TXRDY;
AT91_TWI_UNLOCK(sc);
@@ -229,191 +227,196 @@
return;
}
-static int
-at91_twi_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
+static int
+at91_twi_wait_stop_done(struct at91_twi_softc *sc)
+{
+ int err = 0;
+
+ while (!(RD4(sc, TWI_SR) & TWI_SR_TXCOMP))
+ continue;
+ return (err);
+}
+
+/*
+ * Stop the transfer by entering a STOP state on the iic bus. For read
+ * operations, we've already entered the STOP state, since we need to do
+ * that to read the last character. For write operations, we need to
+ * wait for the TXCOMP bit to turn on before returning.
+ */
+static int
+at91_twi_stop(device_t dev)
{
struct at91_twi_softc *sc;
+ int err = 0;
- sc = CDEV2SOFTC(dev);
- AT91_TWI_LOCK(sc);
- if (!(sc->flags & OPENED)) {
- sc->flags |= OPENED;
- WR4(sc, TWI_IER, TWI_SR_TXCOMP | TWI_SR_RXRDY | TWI_SR_TXRDY |
- TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_NACK);
+ sc = device_get_softc(dev);
+ if (sc->sc_started) {
+ WR4(sc, TWI_CR, TWI_CR_STOP);
+ err = at91_twi_wait_stop_done(sc);
}
- AT91_TWI_UNLOCK(sc);
- return (0);
+ return (err);
}
+/*
+ * enter a START condition without requiring the device to be in a STOP
+ * state.
+ */
static int
-at91_twi_close(struct cdev *dev, int fflag, int devtype, struct thread *td)
+at91_twi_repeated_start(device_t dev, u_char slave, int timeout)
{
struct at91_twi_softc *sc;
- sc = CDEV2SOFTC(dev);
- AT91_TWI_LOCK(sc);
- sc->flags &= ~OPENED;
- WR4(sc, TWI_IDR, TWI_SR_TXCOMP | TWI_SR_RXRDY | TWI_SR_TXRDY |
- TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_NACK);
- AT91_TWI_UNLOCK(sc);
+ sc = device_get_softc(dev);
+ WR4(sc, TWI_MMR, TWI_MMR_DADR(slave));
+ WR4(sc, TWI_CR, TWI_CR_START);
+ sc->sc_started = 1;
return (0);
}
-
+/*
+ * enter a START condition from an idle state.
+ */
static int
-at91_twi_read_master(struct at91_twi_softc *sc, struct at91_twi_io *xfr)
+at91_twi_start(device_t dev, u_char slave, int timeout)
{
- uint8_t *walker;
- uint8_t buffer[256];
- size_t len;
- int err = 0;
+ struct at91_twi_softc *sc;
- if (xfr->xfer_len > sizeof(buffer))
- return (EINVAL);
- walker = buffer;
- len = xfr->xfer_len;
- RD4(sc, TWI_RHR);
- // Master mode, with the right address and interal addr size
- WR4(sc, TWI_MMR, TWI_MMR_IADRSZ(xfr->iadrsz) | TWI_MMR_MREAD |
- TWI_MMR_DADR(xfr->dadr));
- WR4(sc, TWI_IADR, xfr->iadr);
+ sc = device_get_softc(dev);
+ WR4(sc, TWI_MMR, TWI_MMR_DADR(slave));
WR4(sc, TWI_CR, TWI_CR_START);
- while (len-- > 1) {
- while (!(sc->flags & RXRDY)) {
- err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twird",
- 0);
- if (err)
- return (err);
- }
- sc->flags &= ~RXRDY;
- *walker++ = RD4(sc, TWI_RHR) & 0xff;
- }
- WR4(sc, TWI_CR, TWI_CR_STOP);
- while (!(sc->flags & TXCOMP)) {
- err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twird2", 0);
- if (err)
- return (err);
- }
- sc->flags &= ~TXCOMP;
- *walker = RD4(sc, TWI_RHR) & 0xff;
- if (xfr->xfer_buf) {
- AT91_TWI_UNLOCK(sc);
- err = copyout(buffer, xfr->xfer_buf, xfr->xfer_len);
- AT91_TWI_LOCK(sc);
- }
- return (err);
+ sc->sc_started = 1;
+ return (0);
}
static int
-at91_twi_write_master(struct at91_twi_softc *sc, struct at91_twi_io *xfr)
+at91_twi_write(device_t dev, char *buf, int len, int *sent, int timeout /* us */)
{
+ struct at91_twi_softc *sc;
uint8_t *walker;
- uint8_t buffer[256];
- size_t len;
- int err;
+ int err = 0;
- if (xfr->xfer_len > sizeof(buffer))
- return (EINVAL);
- walker = buffer;
- len = xfr->xfer_len;
- AT91_TWI_UNLOCK(sc);
- err = copyin(xfr->xfer_buf, buffer, xfr->xfer_len);
+ walker = buf;
+ sc = device_get_softc(dev);
+ WR4(sc, TWI_MMR, TWI_MMR_MWRITE | RD4(sc, TWI_MMR));
AT91_TWI_LOCK(sc);
- if (err)
- return (err);
- /* Setup the xfr for later readback */
- xfr->xfer_buf = 0;
- xfr->xfer_len = 1;
+ WR4(sc, TWI_IER, TWI_SR_TXRDY);
while (len--) {
- WR4(sc, TWI_MMR, TWI_MMR_IADRSZ(xfr->iadrsz) | TWI_MMR_MWRITE |
- TWI_MMR_DADR(xfr->dadr));
- WR4(sc, TWI_IADR, xfr->iadr++);
WR4(sc, TWI_THR, *walker++);
- WR4(sc, TWI_CR, TWI_CR_START);
- /*
- * If we get signal while waiting for TXRDY, make sure we
- * try to stop this device
- */
while (!(sc->flags & TXRDY)) {
err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twiwr",
0);
if (err)
- break;
+ goto errout;
}
- WR4(sc, TWI_CR, TWI_CR_STOP);
- if (err)
- return (err);
- while (!(sc->flags & TXCOMP)) {
- err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twiwr2",
+ }
+errout:;
+ WR4(sc, TWI_IDR, TWI_SR_TXRDY);
+ AT91_TWI_UNLOCK(sc);
+ return (err);
+}
+
+static int
+at91_twi_read(device_t dev, char *buf, int len, int *read, int last,
+ int delay /* us */)
+{
+ struct at91_twi_softc *sc;
+ char *walker;
+ int err = 0;
+
+ walker = buf;
+ sc = device_get_softc(dev);
+ AT91_TWI_LOCK(sc);
+ WR4(sc, TWI_MMR, ~TWI_MMR_MWRITE & RD4(sc, TWI_MMR));
+ WR4(sc, TWI_IER, TWI_SR_RXRDY);
+ while (len-- > 0) {
+ err = 0;
+ while (!(sc->flags & RXRDY)) {
+ err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twird",
0);
if (err)
- return (err);
+ goto errout;
}
- /* Readback */
- at91_twi_read_master(sc, xfr);
+ sc->flags &= ~RXRDY;
+ *walker++ = RD4(sc, TWI_RHR) & 0xff;
+ if (len == 1 && last)
+ break;
}
+ if (!last)
+ goto errout;
+ WR4(sc, TWI_CR, TWI_CR_STOP);
+ err = at91_twi_wait_stop_done(sc);
+ *walker = RD4(sc, TWI_RHR) & 0xff;
+ if (read)
+ *read = walker - buf;
+ sc->sc_started = 0;
+errout:;
+ WR4(sc, TWI_IDR, TWI_SR_RXRDY);
+ AT91_TWI_UNLOCK(sc);
return (err);
}
static int
-at91_twi_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
- struct thread *td)
+at91_twi_rst_card(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
{
- int err = 0;
struct at91_twi_softc *sc;
+ int ckdiv, rate;
- sc = CDEV2SOFTC(dev);
- AT91_TWI_LOCK(sc);
- while (sc->flags & XFER_PENDING) {
- err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH,
- "twiwait", 0);
- if (err) {
- AT91_TWI_UNLOCK(sc);
- return (err);
- }
- }
- sc->flags |= XFER_PENDING;
+ sc = device_get_softc(dev);
+ if (oldaddr)
+ *oldaddr = sc->twi_addr;
+ if (addr != 0)
+ sc->twi_addr = 0;
+ else
+ sc->twi_addr = addr;
+
+ rate = 1;
+
+ /*
+ * 8 * is because "rate == 1" -> 4 clocks down, 4 clocks up. The
+ * speeds are for 1.5kb/s, 45kb/s and 90kb/s.
+ */
+ switch (speed) {
+ case IIC_SLOW:
+ ckdiv = 8 * AT91C_MASTER_CLOCK / 1500;
+ break;
+
+ case IIC_FAST:
+ ckdiv = 8 * AT91C_MASTER_CLOCK / 45000;
+ break;
- switch (cmd)
- {
- case TWIIOCXFER:
- {
- struct at91_twi_io *xfr = (struct at91_twi_io *)data;
- switch (xfr->type)
- {
- case TWI_IO_READ_MASTER:
- err = at91_twi_read_master(sc, xfr);
- break;
- case TWI_IO_WRITE_MASTER:
- err = at91_twi_write_master(sc, xfr);
- break;
- default:
- err = EINVAL;
- break;
- }
+ case IIC_UNKNOWN:
+ case IIC_FASTEST:
+ default:
+ ckdiv = 8 * AT91C_MASTER_CLOCK / 90000;
break;
}
- case TWIIOCSETCLOCK:
- {
- struct at91_twi_clock *twick = (struct at91_twi_clock *)data;
+ sc->cwgr = TWI_CWGR_CKDIV(ckdiv) | TWI_CWGR_CHDIV(TWI_CWGR_DIV(rate)) |
+ TWI_CWGR_CLDIV(TWI_CWGR_DIV(rate));
+ WR4(sc, TWI_CR, TWI_CR_SWRST);
+ WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
+ WR4(sc, TWI_CWGR, sc->cwgr);
+
+ return EIO;
+}
+
+static int
+at91_twi_callback(device_t dev, int index, caddr_t *data)
+{
+ int error = 0;
+
+ switch (index) {
+ case IIC_REQUEST_BUS:
+ break;
- sc->cwgr = TWI_CWGR_CKDIV(twick->ckdiv) |
- TWI_CWGR_CHDIV(TWI_CWGR_DIV(twick->high_rate)) |
- TWI_CWGR_CLDIV(TWI_CWGR_DIV(twick->low_rate));
- WR4(sc, TWI_CR, TWI_CR_SWRST);
- WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
- WR4(sc, TWI_CWGR, sc->cwgr);
+ case IIC_RELEASE_BUS:
break;
- }
+
default:
- err = ENOTTY;
- break;
+ error = EINVAL;
}
- sc->flags &= ~XFER_PENDING;
- AT91_TWI_UNLOCK(sc);
- wakeup(sc);
- return err;
+
+ return (error);
}
static device_method_t at91_twi_methods[] = {
@@ -422,6 +425,14 @@
DEVMETHOD(device_attach, at91_twi_attach),
DEVMETHOD(device_detach, at91_twi_detach),
+ /* iicbus interface */
+ DEVMETHOD(iicbus_callback, at91_twi_callback),
+ DEVMETHOD(iicbus_repeated_start, at91_twi_repeated_start),
+ DEVMETHOD(iicbus_start, at91_twi_start),
+ DEVMETHOD(iicbus_stop, at91_twi_stop),
+ DEVMETHOD(iicbus_write, at91_twi_write),
+ DEVMETHOD(iicbus_read, at91_twi_read),
+ DEVMETHOD(iicbus_reset, at91_twi_rst_card),
{ 0, 0 }
};
==== //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/at91/at91_usartreg.h#2 (text) ====
@@ -22,30 +22,30 @@
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-/* $FreeBSD: src/sys/arm/at91/at91_usartreg.h,v 1.1 2006/02/04 23:32:13 imp Exp $ */
+/* $FreeBSD: src/sys/arm/at91/at91_usartreg.h,v 1.2 2006/04/06 04:29:24 imp Exp $ */
#ifndef AT91USARTREG_H_
#define AT91USARTREG_H_
#define USART_CR 0x00 /* Control register */
-#define USART_CR_RSTRX (1 << 2) /* Reset Receiver */
-#define USART_CR_RSTTX (1 << 3) /* Reset Transmitter */
-#define USART_CR_RXEN (1 << 4) /* Receiver Enable */
-#define USART_CR_RXDIS (1 << 5) /* Receiver Disable */
-#define USART_CR_TXEN (1 << 6) /* Transmitter Enable */
-#define USART_CR_TXDIS (1 << 7) /* Transmitter Disable */
-#define USART_CR_RSTSTA (1 << 8) /* Reset Status Bits */
-#define USART_CR_STTBRK (1 << 9) /* Start Break */
-#define USART_CR_STPBRK (1 << 10) /* Stop Break */
-#define USART_CR_STTTO (1 << 11) /* Start Time-out */
-#define USART_CR_SENDA (1 << 12) /* Send Address */
-#define USART_CR_RSTIT (1 << 13) /* Reset Iterations */
-#define USART_CR_RSTNACK (1 << 14) /* Reset Non Acknowledge */
-#define USART_CR_RETTO (1 << 15) /* Rearm Time-out */
-#define USART_CR_DTREN (1 << 16) /* Data Terminal ready Enable */
-#define USART_CR_DTRDIS (1 << 17) /* Data Terminal ready Disable */
-#define USART_CR_RTSEN (1 << 18) /* Request to Send enable */
-#define USART_CR_RTSDIS (1 << 19) /* Request to Send Disable */
+#define USART_CR_RSTRX (1UL << 2) /* Reset Receiver */
+#define USART_CR_RSTTX (1UL << 3) /* Reset Transmitter */
+#define USART_CR_RXEN (1UL << 4) /* Receiver Enable */
+#define USART_CR_RXDIS (1UL << 5) /* Receiver Disable */
+#define USART_CR_TXEN (1UL << 6) /* Transmitter Enable */
+#define USART_CR_TXDIS (1UL << 7) /* Transmitter Disable */
+#define USART_CR_RSTSTA (1UL << 8) /* Reset Status Bits */
+#define USART_CR_STTBRK (1UL << 9) /* Start Break */
+#define USART_CR_STPBRK (1UL << 10) /* Stop Break */
+#define USART_CR_STTTO (1UL << 11) /* Start Time-out */
+#define USART_CR_SENDA (1UL << 12) /* Send Address */
+#define USART_CR_RSTIT (1UL << 13) /* Reset Iterations */
+#define USART_CR_RSTNACK (1UL << 14) /* Reset Non Acknowledge */
+#define USART_CR_RETTO (1UL << 15) /* Rearm Time-out */
+#define USART_CR_DTREN (1UL << 16) /* Data Terminal ready Enable */
+#define USART_CR_DTRDIS (1UL << 17) /* Data Terminal ready Disable */
+#define USART_CR_RTSEN (1UL << 18) /* Request to Send enable */
+#define USART_CR_RTSDIS (1UL << 19) /* Request to Send Disable */
#define USART_MR 0x04 /* Mode register */
#define USART_MR_MODE_NORMAL 0 /* Normal/Async/3-wire rs-232 */
@@ -91,28 +91,28 @@
#define USART_IMR 0x10 /* Interrupt mask register */
#define USART_CSR 0x14 /* Channel status register */
-#define USART_CSR_RXRDY (1U << 0) /* Receiver ready */
-#define USART_CSR_TXRDY (1U << 1) /* Transmitter ready */
-#define USART_CSR_RXBRK (1U << 2) /* Break received */
-#define USART_CSR_ENDRX (1U << 3) /* End of Transfer RX from PDC */
-#define USART_CSR_ENDTX (1U << 4) /* End of Transfer TX from PDC */
-#define USART_CSR_OVRE (1U << 5) /* Overrun error */
-#define USART_CSR_FRAME (1U << 6) /* Framing error */
-#define USART_CSR_PARE (1U << 7) /* Parity Error */
-#define USART_CSR_TIMEOUT (1U << 8) /* Timeout since start-timeout */
-#define USART_CSR_TXEMPTY (1U << 9) /* Transmitter empty */
-#define USART_CSR_ITERATION (1U << 10) /* max repetitions since RSIT */
-#define USART_CSR_TXBUFE (1U << 11) /* Buffer empty from PDC */
-#define USART_CSR_RXBUFF (1U << 12) /* Buffer full from PDC */
-#define USART_CSR_NACK (1U << 13) /* NACK since last RSTNACK */
-#define USART_CSR_RIIC (1U << 16) /* RI delta since last csr read */
-#define USART_CSR_DSRIC (1U << 17) /* DSR delta */
-#define USART_CSR_DCDIC (1U << 18) /* DCD delta */
-#define USART_CSR_CTSIC (1U << 19) /* CTS delta */
-#define USART_CSR_RI (1U << 20) /* RI status */
-#define USART_CSR_DSR (1U << 21) /* DSR status */
-#define USART_CSR_DCD (1U << 22) /* DCD status */
-#define USART_CSR_CTS (1U << 23) /* CTS status */
+#define USART_CSR_RXRDY (1UL << 0) /* Receiver ready */
+#define USART_CSR_TXRDY (1UL << 1) /* Transmitter ready */
+#define USART_CSR_RXBRK (1UL << 2) /* Break received */
+#define USART_CSR_ENDRX (1UL << 3) /* End of Transfer RX from PDC */
+#define USART_CSR_ENDTX (1UL << 4) /* End of Transfer TX from PDC */
+#define USART_CSR_OVRE (1UL << 5) /* Overrun error */
+#define USART_CSR_FRAME (1UL << 6) /* Framing error */
+#define USART_CSR_PARE (1UL << 7) /* Parity Error */
+#define USART_CSR_TIMEOUT (1UL << 8) /* Timeout since start-timeout */
+#define USART_CSR_TXEMPTY (1UL << 9) /* Transmitter empty */
+#define USART_CSR_ITERATION (1UL << 10) /* max repetitions since RSIT */
+#define USART_CSR_TXBUFE (1UL << 11) /* Buffer empty from PDC */
+#define USART_CSR_RXBUFF (1UL << 12) /* Buffer full from PDC */
+#define USART_CSR_NACK (1UL << 13) /* NACK since last RSTNACK */
+#define USART_CSR_RIIC (1UL << 16) /* RI delta since last csr read */
+#define USART_CSR_DSRIC (1UL << 17) /* DSR delta */
+#define USART_CSR_DCDIC (1UL << 18) /* DCD delta */
+#define USART_CSR_CTSIC (1UL << 19) /* CTS delta */
+#define USART_CSR_RI (1UL << 20) /* RI status */
+#define USART_CSR_DSR (1UL << 21) /* DSR status */
+#define USART_CSR_DCD (1UL << 22) /* DCD status */
+#define USART_CSR_CTS (1UL << 23) /* CTS status */
#define USART_RHR 0x18 /* Receiver holding register */
#define USART_THR 0x1c /* Transmitter holding register */
@@ -125,24 +125,4 @@
/* 0x48 reserved */
#define USART_IFR 0x48 /* IrDA filter register */
-
-#define UART_RXRDY (0x1 << 0) /* RXRDY Interrupt */
-#define UART_TXRDY (0x1 << 1) /* TXRDY Interrupt */
-#define UART_RXBRK (0x1 << 2) /* Break Received/End of Break */
-#define UART_ENDRX (0x1 << 3) /* End of Receive Transfer Interrupt */
-#define UART_ENDTX (0x1 << 4) /* End of Transmit Interrupt */
-#define UART_OVRE (0x1 << 5) /* Overrun Interrupt */
-#define UART_FRAME (0x1 << 6) /* Framing Error Interrupt */
-#define UART_PARE (0x1 << 7) /* Parity Error Interrupt */
-#define UART_TIMEOUT ( 0x1 << 8) /* (USART) Receiver Time-out */
-#define UART_TXEMPTY ( 0x1 << 9) /* (USART) TXEMPTY Interrupt */
-#define UART_ITERATION ( 0x1 << 10) /* (USART) Max number of Repetitions Reached */
-#define UART_TXBUFE ( 0x1 << 11) /* (USART) TXBUFE Interrupt */
-#define UART_RXBUFF ( 0x1 << 12) /* (USART) RXBUFF Interrupt */
-#define UART_NACK ( 0x1 << 13) /* (USART) Non Acknowledge */
-#define UART_RIIC ( 0x1 << 16) /* (USART) Ring INdicator Input Change Flag */
-#define AT91RM92_US_DSRIC ( 0x1 << 17) /* (USART) Data Set Ready Input Change Flag */
-#define AT91RM92_US_DCDIC ( 0x1 << 18) /* (USART) Data Carrier Flag */
-#define AT91RM92_US_CTSIC ( 0x1 << 19) /* (USART) Clear To Send Input Change Flag */
-
#endif /* AT91RM92REG_H_ */
==== //depot/projects/trustedbsd/acl_nfsv4/src/sys/arm/at91/if_ate.c#2 (text) ====
@@ -33,7 +33,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/arm/at91/if_ate.c,v 1.5 2006/03/18 01:43:25 imp Exp $");
+__FBSDID("$FreeBSD: src/sys/arm/at91/if_ate.c,v 1.6 2006/04/06 04:30:23 imp Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -86,13 +86,14 @@
struct callout tick_ch; /* Tick callout */
bus_dma_tag_t mtag; /* bus dma tag for mbufs */
bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS];
+ struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */
bus_dma_tag_t rxtag;
bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS];
+ void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */
+ int rx_buf_ptr;
bus_dma_tag_t rx_desc_tag;
bus_dmamap_t rx_desc_map;
int txcur; /* current tx map pointer */
- struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */
- struct mbuf *rx_mbuf[ATE_MAX_RX_BUFFERS]; /* RX mbufs */
bus_addr_t rx_desc_phys;
eth_rx_desc_t *rx_descs;
struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
@@ -241,6 +242,30 @@
sc->rx_desc_phys = segs[0].ds_addr;
}
+static void
+ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
+{
+ struct ate_softc *sc;
+ int i;
+
+ if (error != 0)
+ return;
+ sc = (struct ate_softc *)arg;
+ i = sc->rx_buf_ptr;
+
+ /*
+ * For the last buffer, set the wrap bit so the controller
+ * restarts from the first descriptor.
+ */
+ if (i == ATE_MAX_RX_BUFFERS - 1)
+ sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT;
+ else
+ sc->rx_descs[i].addr = segs[0].ds_addr;
+ sc->rx_descs[i].status = 0;
+ /* Flush the memory in the mbuf */
+ bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD);
+}
+
/*
* Compute the multicast filter for this device using the standard
* algorithm. I wonder why this isn't in ether somewhere as a lot
@@ -275,10 +300,8 @@
* advantage of that. Locks here are to avoid LOR with the
* IF_ADDR_LOCK, but might not be strictly necessary.
*/
- ATE_LOCK(sc);
WR4(sc, ETH_HSL, mcaf[0]);
WR4(sc, ETH_HSH, mcaf[1]);
- ATE_UNLOCK(sc);
}
static int
@@ -342,33 +365,21 @@
if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs,
BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0)
goto errout;
- if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map,
+ if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map,
sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t),
ate_getaddr, sc, 0) != 0)
goto errout;
/* XXX TODO(5) Put this in ateinit_locked? */
for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) {
- bus_dma_segment_t seg;
- int nsegs;
-
- sc->rx_mbuf[i] = m_getcl(M_WAITOK, MT_DATA, M_PKTHDR);
- sc->rx_mbuf[i]->m_len = sc->rx_mbuf[i]->m_pkthdr.len =
>>> TRUNCATED FOR MAIL (1000 lines) <<<
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