PERFORCE change 94883 for review
Warner Losh
imp at FreeBSD.org
Mon Apr 10 03:10:00 UTC 2006
http://perforce.freebsd.org/chv.cgi?CH=94883
Change 94883 by imp at imp_hammer on 2006/04/10 03:09:30
Simplify. This bums us 22 more bytes.
Affected files ...
.. //depot/projects/arm/src/sys/boot/arm/kb920x/boot0/at91rm9200_lowlevel.c#2 edit
Differences ...
==== //depot/projects/arm/src/sys/boot/arm/kb920x/boot0/at91rm9200_lowlevel.c#2 (text+ko) ====
@@ -24,6 +24,8 @@
#include "at91rm9200_lowlevel.h"
#include "debug_io.h"
+#define BAUD 115200
+
/* ****************************** GLOBALS *************************************/
@@ -31,59 +33,6 @@
#define AT91C_US_ASYNC_MODE (AT91C_US_USMODE_NORMAL + AT91C_US_NBSTOP_1_BIT + AT91C_US_PAR_NONE + AT91C_US_CHRL_8_BITS + AT91C_US_CLKS_CLOCK)
-
-/*
- * .KB_C_FN_DEFINITION_START
- * void Enable_Debug_USART(AT91PS_USART pUSART)
- * This private function enables and configures the debug uart.
- * .KB_C_FN_DEFINITION_END
- */
-/*
-static void Enable_Debug_USART(AT91PS_USART pUSART) {
-
- AT91PS_PDC pPDC = (AT91PS_PDC)&(pUSART->US_RPR);
- AT91PS_PIO pPio = (AT91PS_PIO)AT91C_BASE_PIOA;
-
- pPio->PIO_ASR =
- ((unsigned)AT91C_PA31_DTXD) | ((unsigned)AT91C_PA30_DRXD);
- pPio->PIO_BSR = 0;
- pPio->PIO_PDR =
- ((unsigned)AT91C_PA31_DTXD) | ((unsigned)AT91C_PA30_DRXD);
-
- pUSART->US_IDR = (unsigned int) -1;
-
- pUSART->US_CR =
- AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
-
- pUSART->US_BRGR = ((((AT91C_MASTER_CLOCK*10)/(115200*16))+5)/10);
-
- pUSART->US_TTGR = 0;
-
- pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
- pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
-
- pPDC->PDC_TNPR = 0;
- pPDC->PDC_TNCR = 0;
-
- pPDC->PDC_RNPR = 0;
- pPDC->PDC_RNCR = 0;
-
- pPDC->PDC_TPR = 0;
- pPDC->PDC_TCR = 0;
-
- pPDC->PDC_RPR = 0;
- pPDC->PDC_RCR = 0;
-
- pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
- pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
-
- pUSART->US_MR = AT91C_US_ASYNC_MODE;
-
- pUSART->US_CR = AT91C_US_TXEN;
- pUSART->US_CR = AT91C_US_RXEN;
-}
-*/
-
/* ************************** GLOBAL FUNCTIONS ********************************/
@@ -93,8 +42,9 @@
* Returns a value read from the RTC for use as a rough seconds counter.
* .KB_C_FN_DEFINITION_END
*/
-unsigned GetSeconds(void) {
- return (((AT91PS_RTC)AT91C_BASE_RTC)->RTC_TIMR & AT91C_RTC_SEC);
+unsigned GetSeconds(void)
+{
+ return (AT91C_BASE_RTC->RTC_TIMR & AT91C_RTC_SEC);
}
@@ -104,7 +54,12 @@
* If no system config info is found, config the board for default parameters.
* .KB_C_FN_DEFINITION_END
*/
-void DefaultSystemInit(void) {
+void DefaultSystemInit(void)
+{
+ AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU;
+ AT91PS_PDC pPDC = (AT91PS_PDC)&(pUSART->US_RPR);
+ AT91PS_PIO pPio = AT91C_BASE_PIOA;
+
register unsigned value;
int i;
@@ -121,7 +76,7 @@
// set PLLA = 180MHz
// assume main osc = 10Mhz
// div = 5 , out = 2 (150MHz = 240MHz)
- value = ((AT91PS_CKGR)AT91C_BASE_CKGR)->CKGR_PLLAR;
+ value = AT91C_BASE_CKGR->CKGR_PLLAR;
value &= ~AT91C_CKGR_DIVA;
value &= ~AT91C_CKGR_OUTA;
#ifdef USE_80P_20M_CLOCKS
@@ -130,23 +85,23 @@
value |= (OSC_MAIN_FREQ_DIV | AT91C_CKGR_OUTA_2);
#endif
value |= AT91C_CKGR_SRCA;
- ((AT91PS_CKGR)AT91C_BASE_CKGR)->CKGR_PLLAR = value;
+ AT91C_BASE_CKGR->CKGR_PLLAR = value;
// mul = 90
- value = ((AT91PS_CKGR)AT91C_BASE_CKGR)->CKGR_PLLAR;
+ value = AT91C_BASE_CKGR->CKGR_PLLAR;
value &= ~AT91C_CKGR_MULA;
#ifdef USE_80P_20M_CLOCKS
value |= (39 << 16);
#else
value |= (89 << 16);
#endif
- ((AT91PS_CKGR)AT91C_BASE_CKGR)->CKGR_PLLAR = value;
+ AT91C_BASE_CKGR->CKGR_PLLAR = value;
// wait for lock
- while (!((((AT91PS_PMC)AT91C_BASE_PMC)->PMC_SR) & AT91C_PMC_LOCKA)) ;
+ while (!((AT91C_BASE_PMC->PMC_SR) & AT91C_PMC_LOCKA)) ;
// change divider = 3, pres = 1
- value = ((AT91PS_PMC)AT91C_BASE_PMC)->PMC_MCKR;
+ value = AT91C_BASE_PMC->PMC_MCKR;
value &= ~AT91C_PMC_MDIV;
#ifdef USE_80P_20M_CLOCKS
value |= AT91C_PMC_MDIV_4;
@@ -155,28 +110,18 @@
#endif
value &= ~AT91C_PMC_PRES;
value |= AT91C_PMC_PRES_CLK;
- ((AT91PS_PMC)AT91C_BASE_PMC)->PMC_MCKR = value;
+ AT91C_BASE_PMC->PMC_MCKR = value;
// wait for update
- while (!((((AT91PS_PMC)AT91C_BASE_PMC)->PMC_SR) & AT91C_PMC_MCKRDY)) ;
+ while (!((AT91C_BASE_PMC->PMC_SR) & AT91C_PMC_MCKRDY)) ;
// change CSS = PLLA
value &= ~AT91C_PMC_CSS;
value |= AT91C_PMC_CSS_PLLA_CLK;
- ((AT91PS_PMC)AT91C_BASE_PMC)->PMC_MCKR = value;
+ AT91C_BASE_PMC->PMC_MCKR = value;
// wait for update
- while (!((((AT91PS_PMC)AT91C_BASE_PMC)->PMC_SR) & AT91C_PMC_MCKRDY)) ;
-
- // setup flash access (allow ample margin)
- // 9 wait states, 1 setup, 1 hold, 1 float for 8-bit device
- ((AT91PS_SMC2)AT91C_BASE_SMC2)->SMC2_CSR[0] =
- AT91C_SMC2_WSEN |
- (9 & AT91C_SMC2_NWS) |
- ((1 << 8) & AT91C_SMC2_TDF) |
- AT91C_SMC2_DBW_8 |
- ((1 << 24) & AT91C_SMC2_RWSETUP) |
- ((1 << 29) & AT91C_SMC2_RWHOLD);
+ while (!((AT91C_BASE_PMC->PMC_SR) & AT91C_PMC_MCKRDY)) ;
// setup SDRAM access
// EBI chip-select register (CS1 = SDRAM controller)
@@ -190,9 +135,9 @@
value = ((AT91PS_EBI)AT91C_BASE_EBI)->EBI_CSA;
value &= ~AT91C_EBI_CS1A;
value |= AT91C_EBI_CS1A_SDRAMC;
- ((AT91PS_EBI)AT91C_BASE_EBI)->EBI_CSA = value;
+ AT91C_BASE_EBI->EBI_CSA = value;
- ((AT91PS_SDRC)AT91C_BASE_SDRC)->SDRC_CR =
+ AT91C_BASE_SDRC->SDRC_CR =
AT91C_SDRC_NC_9 |
AT91C_SDRC_NR_13 |
AT91C_SDRC_NB_4_BANKS |
@@ -205,11 +150,11 @@
((6 << 27) & AT91C_SDRC_TXSR);
- ((AT91PS_SDRC)AT91C_BASE_SDRC)->SDRC_MR =
+ AT91C_BASE_SDRC->SDRC_MR =
AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_PRCGALL_CMD;
*(unsigned short*)SDRAM_BASE = 0;
- ((AT91PS_SDRC)AT91C_BASE_SDRC)->SDRC_MR =
+ AT91C_BASE_SDRC->SDRC_MR =
AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_RFSH_CMD;
*(unsigned short*)SDRAM_BASE = 0;
*(unsigned short*)SDRAM_BASE = 0;
@@ -220,64 +165,45 @@
*(unsigned short*)SDRAM_BASE = 0;
*(unsigned short*)SDRAM_BASE = 0;
- ((AT91PS_SDRC)AT91C_BASE_SDRC)->SDRC_MR =
+ AT91C_BASE_SDRC->SDRC_MR =
AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_LMR_CMD;
*(unsigned short*)SDRAM_BASE = 0;
- ((AT91PS_SDRC)AT91C_BASE_SDRC)->SDRC_TR =
- 7 * AT91C_MASTER_CLOCK / 1000000;
+ AT91C_BASE_SDRC->SDRC_TR = 7 * AT91C_MASTER_CLOCK / 1000000;
*(unsigned short*)SDRAM_BASE = 0;
- ((AT91PS_SDRC)AT91C_BASE_SDRC)->SDRC_MR =
- AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_NORMAL_CMD;
+ AT91C_BASE_SDRC->SDRC_MR =
+ AT91C_SDRC_DBW_16_BITS | AT91C_SDRC_MODE_NORMAL_CMD;
*(unsigned short*)SDRAM_BASE = 0;
// Configure DBGU -use local routine optimized for space
- // Enable_Debug_USART((AT91PS_USART)AT91C_BASE_DBGU);
- {
- AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU;
- AT91PS_PDC pPDC = (AT91PS_PDC)&(pUSART->US_RPR);
- AT91PS_PIO pPio = (AT91PS_PIO)AT91C_BASE_PIOA;
+ pPio->PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;
+ pPio->PIO_BSR = 0;
+ pPio->PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;
+ pUSART->US_IDR = (unsigned int) -1;
+ pUSART->US_CR =
+ AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
+ pUSART->US_BRGR = ((((AT91C_MASTER_CLOCK*10)/(BAUD*16))+5)/10);
+ pUSART->US_TTGR = 0;
+ pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+ pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+ pPDC->PDC_TNPR = 0;
+ pPDC->PDC_TNCR = 0;
- pPio->PIO_ASR =
- ((unsigned)AT91C_PA31_DTXD) | ((unsigned)AT91C_PA30_DRXD);
- pPio->PIO_BSR = 0;
- pPio->PIO_PDR =
- ((unsigned)AT91C_PA31_DTXD) | ((unsigned)AT91C_PA30_DRXD);
+ pPDC->PDC_RNPR = 0;
+ pPDC->PDC_RNCR = 0;
- pUSART->US_IDR = (unsigned int) -1;
+ pPDC->PDC_TPR = 0;
+ pPDC->PDC_TCR = 0;
- pUSART->US_CR =
- AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
+ pPDC->PDC_RPR = 0;
+ pPDC->PDC_RCR = 0;
- pUSART->US_BRGR = ((((AT91C_MASTER_CLOCK*10)/(115200*16))+5)/10);
+ pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+ pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
- pUSART->US_TTGR = 0;
-
- pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
- pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
-
- pPDC->PDC_TNPR = 0;
- pPDC->PDC_TNCR = 0;
-
- pPDC->PDC_RNPR = 0;
- pPDC->PDC_RNCR = 0;
-
- pPDC->PDC_TPR = 0;
- pPDC->PDC_TCR = 0;
-
- pPDC->PDC_RPR = 0;
- pPDC->PDC_RCR = 0;
-
- pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
- pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
-
- pUSART->US_MR = AT91C_US_ASYNC_MODE;
-
- pUSART->US_CR = AT91C_US_TXEN;
- pUSART->US_CR = AT91C_US_RXEN;
- }
- while (1)
- DebugPutc('C');
+ pUSART->US_MR = AT91C_US_ASYNC_MODE;
+ pUSART->US_CR = AT91C_US_TXEN;
+ pUSART->US_CR = AT91C_US_RXEN;
}
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