PERFORCE change 75278 for review
John Baldwin
jhb at FreeBSD.org
Fri Apr 15 15:02:33 PDT 2005
http://perforce.freebsd.org/chv.cgi?CH=75278
Change 75278 by jhb at jhb_slimer on 2005/04/15 22:01:31
IFC @75276.
Affected files ...
.. //depot/projects/smpng/sys/amd64/acpica/madt.c#6 integrate
.. //depot/projects/smpng/sys/amd64/amd64/io_apic.c#7 integrate
.. //depot/projects/smpng/sys/amd64/amd64/mptable.c#8 integrate
.. //depot/projects/smpng/sys/amd64/conf/GENERIC#32 integrate
.. //depot/projects/smpng/sys/amd64/conf/NOTES#15 integrate
.. //depot/projects/smpng/sys/amd64/include/apicvar.h#6 integrate
.. //depot/projects/smpng/sys/amd64/include/bus.h#3 integrate
.. //depot/projects/smpng/sys/amd64/include/bus_amd64.h#8 delete
.. //depot/projects/smpng/sys/amd64/include/legacyvar.h#4 integrate
.. //depot/projects/smpng/sys/amd64/include/tss.h#5 integrate
.. //depot/projects/smpng/sys/amd64/isa/clock.c#12 integrate
.. //depot/projects/smpng/sys/conf/options.amd64#11 integrate
.. //depot/projects/smpng/sys/conf/options.pc98#45 integrate
.. //depot/projects/smpng/sys/dev/ata/ata-all.c#69 integrate
.. //depot/projects/smpng/sys/dev/ata/ata-all.h#36 integrate
.. //depot/projects/smpng/sys/dev/ata/ata-disk.c#49 integrate
.. //depot/projects/smpng/sys/dev/ata/atapi-cam.c#24 integrate
.. //depot/projects/smpng/sys/dev/ata/atapi-cd.c#55 integrate
.. //depot/projects/smpng/sys/dev/ata/atapi-fd.c#27 integrate
.. //depot/projects/smpng/sys/dev/ata/atapi-tape.c#31 integrate
.. //depot/projects/smpng/sys/i386/conf/NOTES#99 integrate
.. //depot/projects/smpng/sys/ia64/ia64/mp_machdep.c#29 integrate
.. //depot/projects/smpng/sys/kern/sched_4bsd.c#49 integrate
.. //depot/projects/smpng/sys/net/if.c#64 integrate
.. //depot/projects/smpng/sys/netgraph/ng_echo.c#4 integrate
.. //depot/projects/smpng/sys/netinet/ip_fw2.c#51 integrate
.. //depot/projects/smpng/sys/netinet/tcp_input.c#70 integrate
.. //depot/projects/smpng/sys/netinet/tcp_sack.c#9 integrate
.. //depot/projects/smpng/sys/netinet/tcp_var.h#36 integrate
.. //depot/projects/smpng/sys/pc98/conf/NOTES#37 integrate
.. //depot/projects/smpng/sys/sys/ata.h#20 integrate
.. //depot/projects/smpng/sys/vm/vm_pageq.c#12 integrate
Differences ...
==== //depot/projects/smpng/sys/amd64/acpica/madt.c#6 (text+ko) ====
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/amd64/acpica/madt.c,v 1.15 2005/02/22 21:52:51 jhb Exp $");
+__FBSDID("$FreeBSD: src/sys/amd64/acpica/madt.c,v 1.16 2005/04/15 18:44:53 peter Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -367,8 +367,6 @@
}
/* First, we run through adding I/O APIC's. */
- if (madt->PCATCompat && !(acpi_quirks & ACPI_Q_MADT_IRQ0))
- ioapic_enable_mixed_mode();
madt_walk_table(madt_parse_apics, NULL);
/* Second, we run through the table tweaking interrupt sources. */
==== //depot/projects/smpng/sys/amd64/amd64/io_apic.c#7 (text+ko) ====
@@ -28,11 +28,10 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/amd64/amd64/io_apic.c,v 1.14 2005/02/28 23:37:35 peter Exp $");
+__FBSDID("$FreeBSD: src/sys/amd64/amd64/io_apic.c,v 1.15 2005/04/15 18:44:53 peter Exp $");
#include "opt_atpic.h"
#include "opt_isa.h"
-#include "opt_no_mixed_mode.h"
#include <sys/param.h>
#include <sys/systm.h>
@@ -62,7 +61,6 @@
#define VECTOR_DISABLED 255
#define DEST_NONE -1
-#define DEST_EXTINT -2
#define TODO printf("%s: not implemented!\n", __func__)
@@ -83,15 +81,6 @@
* IO APIC has a contiguous chunk of the System Interrupt address space.
*/
-/*
- * Direct the ExtINT pin on the first I/O APIC to a logical cluster of
- * CPUs rather than a physical destination of just the BSP.
- *
- * Note: This is disabled by default as test systems seem to croak with it
- * enabled.
-#define ENABLE_EXTINT_LOGICAL_DESTINATION
- */
-
struct ioapic_intsrc {
struct intsrc io_intsrc;
u_int io_intpin:8;
@@ -130,7 +119,6 @@
static void ioapic_resume(struct intsrc *isrc);
static void ioapic_program_destination(struct ioapic_intsrc *intpin);
static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
-static void ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin);
static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
@@ -140,13 +128,7 @@
ioapic_config_intr };
static int bsp_id, current_cluster, logical_clusters, next_ioapic_base;
-static u_int mixed_mode_enabled, next_id, program_logical_dest;
-#if defined(NO_MIXED_MODE) || !defined(DEV_ATPIC)
-static int mixed_mode_active = 0;
-#else
-static int mixed_mode_active = 1;
-#endif
-TUNABLE_INT("hw.apic.mixed_mode", &mixed_mode_active);
+static u_int next_id, program_logical_dest;
static __inline void
_ioapic_eoi_source(struct intsrc *isrc)
@@ -270,12 +252,8 @@
struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
uint32_t low, high, value;
- /*
- * For pins routed via mixed mode or disabled, just ensure that
- * they are masked.
- */
- if (intpin->io_dest == DEST_EXTINT ||
- intpin->io_vector == VECTOR_DISABLED) {
+ /* For disabled pins, just ensure that they are masked. */
+ if (intpin->io_vector == VECTOR_DISABLED) {
low = ioapic_read(io->io_addr,
IOAPIC_REDTBL_LO(intpin->io_intpin));
if ((low & IOART_INTMASK) == IOART_INTMCLR)
@@ -346,8 +324,6 @@
KASSERT(intpin->io_dest != DEST_NONE,
("intpin not assigned to a cluster"));
- KASSERT(intpin->io_dest != DEST_EXTINT,
- ("intpin routed via ExtINT"));
if (bootverbose) {
printf("ioapic%u: routing intpin %u (", io->io_id,
intpin->io_intpin);
@@ -383,8 +359,6 @@
{
struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
- KASSERT(intpin->io_dest != DEST_EXTINT,
- ("ExtINT pin trying to use ioapic enable_intr method"));
if (intpin->io_dest == DEST_NONE) {
ioapic_assign_cluster(intpin);
lapic_enable_intr(intpin->io_vector);
@@ -465,17 +439,6 @@
}
/*
- * APIC enumerators call this function to indicate that the 8259A AT PICs
- * are available and that mixed mode can be used.
- */
-void
-ioapic_enable_mixed_mode(void)
-{
-
- mixed_mode_enabled = 1;
-}
-
-/*
* Allocate and return a logical cluster ID. Note that the first time
* this is called, it returns cluster 0. ioapic_enable_intr() treats
* the two cases of logical_clusters == 0 and logical_clusters == 1 the
@@ -503,11 +466,20 @@
u_int numintr, i;
uint32_t value;
+ /* Map the register window so we can access the device. */
apic = (ioapic_t *)pmap_mapdev(addr, IOAPIC_MEM_REGION);
mtx_lock_spin(&icu_lock);
- numintr = ((ioapic_read(apic, IOAPIC_VER) & IOART_VER_MAXREDIR) >>
- MAXREDIRSHIFT) + 1;
+ value = ioapic_read(apic, IOAPIC_VER);
mtx_unlock_spin(&icu_lock);
+
+ /* If it's version register doesn't seem to work, punt. */
+ if (value == 0xffffff) {
+ pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION);
+ return (NULL);
+ }
+
+ /* Determine the number of vectors and set the APIC ID. */
+ numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
io = malloc(sizeof(struct ioapic) +
numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
io->io_pic = ioapic_template;
@@ -547,12 +519,11 @@
intpin->io_vector = intbase + i;
/*
- * Assume that pin 0 on the first I/O APIC is an ExtINT pin
- * if mixed mode is enabled and an ISA interrupt if not.
+ * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
* Assume that pins 1-15 are ISA interrupts and that all
* other pins are PCI interrupts.
*/
- if (intpin->io_vector == 0 && mixed_mode_enabled)
+ if (intpin->io_vector == 0)
ioapic_set_extint(io, i);
else if (intpin->io_vector < IOAPIC_ISA_INTS) {
intpin->io_bus = APIC_BUS_ISA;
@@ -710,12 +681,7 @@
return (EINVAL);
io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
io->io_pins[pin].io_vector = VECTOR_EXTINT;
-
- /* Enable this pin if mixed mode is available and active. */
- if (mixed_mode_enabled && mixed_mode_active)
- io->io_pins[pin].io_masked = 0;
- else
- io->io_pins[pin].io_masked = 1;
+ io->io_pins[pin].io_masked = 1;
io->io_pins[pin].io_edgetrigger = 1;
io->io_pins[pin].io_activehi = 1;
if (bootverbose)
@@ -790,15 +756,7 @@
ioapic_program_intpin(pin);
if (pin->io_vector >= NUM_IO_INTS)
continue;
- /*
- * Route IRQ0 via the 8259A using mixed mode if mixed mode
- * is available and turned on.
- */
- if (pin->io_vector == 0 && mixed_mode_active &&
- mixed_mode_enabled)
- ioapic_setup_mixed_mode(pin);
- else
- intr_register_source(&pin->io_intsrc);
+ intr_register_source(&pin->io_intsrc);
}
}
@@ -815,38 +773,8 @@
program_logical_dest = 1;
STAILQ_FOREACH(io, &ioapic_list, io_next)
for (i = 0; i < io->io_numintr; i++)
- if (io->io_pins[i].io_dest != DEST_NONE &&
- io->io_pins[i].io_dest != DEST_EXTINT)
+ if (io->io_pins[i].io_dest != DEST_NONE)
ioapic_program_destination(&io->io_pins[i]);
}
SYSINIT(ioapic_destinations, SI_SUB_SMP, SI_ORDER_SECOND,
ioapic_set_logical_destinations, NULL)
-
-/*
- * Support for mixed-mode interrupt sources. These sources route an ISA
- * IRQ through the 8259A's via the ExtINT on pin 0 of the I/O APIC that
- * routes the ISA interrupts. We just ignore the intpins that use this
- * mode and allow the atpic driver to register its interrupt source for
- * that IRQ instead.
- */
-
-static void
-ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin)
-{
- struct ioapic_intsrc *extint;
- struct ioapic *io;
-
- /*
- * Mark the associated I/O APIC intpin as being delivered via
- * ExtINT and enable the ExtINT pin on the I/O APIC if needed.
- */
- intpin->io_dest = DEST_EXTINT;
- io = (struct ioapic *)intpin->io_intsrc.is_pic;
- extint = &io->io_pins[0];
- if (extint->io_vector != VECTOR_EXTINT)
- panic("Can't find ExtINT pin to route through!");
-#ifdef ENABLE_EXTINT_LOGICAL_DESTINATION
- if (extint->io_dest == DEST_NONE)
- ioapic_assign_cluster(extint);
-#endif
-}
==== //depot/projects/smpng/sys/amd64/amd64/mptable.c#8 (text+ko) ====
@@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/amd64/amd64/mptable.c,v 1.235 2005/02/28 23:37:35 peter Exp $");
+__FBSDID("$FreeBSD: src/sys/amd64/amd64/mptable.c,v 1.236 2005/04/15 18:44:53 peter Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -348,7 +348,6 @@
busses[i].bus_type = NOBUS;
/* Second, we run through adding I/O APIC's and busses. */
- ioapic_enable_mixed_mode();
mptable_parse_apics_and_busses();
/* Third, we run through the table tweaking interrupt sources. */
==== //depot/projects/smpng/sys/amd64/conf/GENERIC#32 (text+ko) ====
@@ -16,7 +16,7 @@
# If you are in doubt as to the purpose or necessity of a line, check first
# in NOTES.
#
-# $FreeBSD: src/sys/amd64/conf/GENERIC,v 1.437 2005/04/13 06:00:07 anholt Exp $
+# $FreeBSD: src/sys/amd64/conf/GENERIC,v 1.438 2005/04/15 18:45:07 peter Exp $
machine amd64
cpu HAMMER
@@ -77,7 +77,6 @@
# Workarounds for some known-to-be-broken chipsets (nVidia nForce3-Pro150)
device atpic # 8259A compatability
-options NO_MIXED_MODE # Don't penalize working chipsets
# Linux 32-bit ABI support
options LINPROCFS # Cannot be a module yet.
==== //depot/projects/smpng/sys/amd64/conf/NOTES#15 (text+ko) ====
@@ -4,7 +4,7 @@
# This file contains machine dependent kernel configuration notes. For
# machine independent notes, look in /sys/conf/NOTES.
#
-# $FreeBSD: src/sys/amd64/conf/NOTES,v 1.28 2005/04/08 20:24:45 obrien Exp $
+# $FreeBSD: src/sys/amd64/conf/NOTES,v 1.29 2005/04/15 18:45:07 peter Exp $
#
#
@@ -23,19 +23,10 @@
#
# Notes:
#
-# By default, mixed mode is used to route IRQ0 from the AT timer via
-# the 8259A master PIC through the ExtINT pin on the first I/O APIC.
-# This can be disabled via the NO_MIXED_MODE option. In that case,
-# IRQ0 will be routed via an intpin on the first I/O APIC. Not all
-# motherboards hook IRQ0 up to the first I/O APIC even though their
-# MP table or MADT may claim to do so. That is why mixed mode is
-# enabled by default.
-#
# Optional:
device atpic # Optional legacy pic support
device mptable # Optional MPSPEC mptable support
-options NO_MIXED_MODE # Disable use of mixed mode
#
# Watchdog routines.
==== //depot/projects/smpng/sys/amd64/include/apicvar.h#6 (text+ko) ====
@@ -26,7 +26,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * $FreeBSD: src/sys/amd64/include/apicvar.h,v 1.11 2005/02/28 23:37:35 peter Exp $
+ * $FreeBSD: src/sys/amd64/include/apicvar.h,v 1.12 2005/04/15 18:44:53 peter Exp $
*/
#ifndef _MACHINE_APICVAR_H_
@@ -177,7 +177,6 @@
void apic_register_enumerator(struct apic_enumerator *enumerator);
void *ioapic_create(uintptr_t addr, int32_t id, int intbase);
int ioapic_disable_pin(void *cookie, u_int pin);
-void ioapic_enable_mixed_mode(void);
int ioapic_get_vector(void *cookie, u_int pin);
int ioapic_next_logical_cluster(void);
void ioapic_register(void *cookie);
==== //depot/projects/smpng/sys/amd64/include/bus.h#3 (text+ko) ====
@@ -28,13 +28,1231 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * $FreeBSD: src/sys/amd64/include/bus.h,v 1.12 2003/05/12 02:44:37 peter Exp $
+ * $FreeBSD: src/sys/amd64/include/bus.h,v 1.13 2005/04/15 18:38:59 peter Exp $
+ */
+
+/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */
+
+/*-
+ * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
+ * NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
+ * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Christopher G. Demetriou
+ * for the NetBSD Project.
+ * 4. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _AMD64_BUS_H_
#define _AMD64_BUS_H_
-#include <machine/bus_amd64.h>
+#include <machine/cpufunc.h>
+
+/*
+ * To remain compatible with NetBSD's interface, default to both memio and
+ * pio when neither of them is defined.
+ */
+#if !defined(_AMD64_BUS_PIO_H_) && !defined(_AMD64_BUS_MEMIO_H_)
+#define _AMD64_BUS_PIO_H_
+#define _AMD64_BUS_MEMIO_H_
+#endif
+
+/*
+ * Values for the amd64 bus space tag, not to be used directly by MI code.
+ */
+#define AMD64_BUS_SPACE_IO 0 /* space is i/o space */
+#define AMD64_BUS_SPACE_MEM 1 /* space is mem space */
+
+/*
+ * Bus address and size types
+ */
+typedef uint64_t bus_addr_t;
+typedef uint64_t bus_size_t;
+
+#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF
+#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF
+#define BUS_SPACE_MAXSIZE 0xFFFFFFFF
+#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF
+#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF
+#define BUS_SPACE_MAXADDR 0xFFFFFFFFFFFFFFFFULL
+
+#define BUS_SPACE_UNRESTRICTED (~0)
+
+/*
+ * Access methods for bus resources and address space.
+ */
+typedef uint64_t bus_space_tag_t;
+typedef uint64_t bus_space_handle_t;
+
+/*
+ * Map a region of device bus space into CPU virtual address space.
+ */
+
+static __inline int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
+ bus_size_t size, int flags,
+ bus_space_handle_t *bshp);
+
+static __inline int
+bus_space_map(bus_space_tag_t t __unused, bus_addr_t addr,
+ bus_size_t size __unused, int flags __unused,
+ bus_space_handle_t *bshp)
+{
+
+ *bshp = addr;
+ return (0);
+}
+
+/*
+ * Unmap a region of device bus space.
+ */
+
+static __inline void bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh,
+ bus_size_t size);
+
+static __inline void
+bus_space_unmap(bus_space_tag_t t __unused, bus_space_handle_t bsh __unused,
+ bus_size_t size __unused)
+{
+}
+
+/*
+ * Get a new handle for a subregion of an already-mapped area of bus space.
+ */
+
+static __inline int bus_space_subregion(bus_space_tag_t t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, bus_size_t size,
+ bus_space_handle_t *nbshp);
+
+static __inline int
+bus_space_subregion(bus_space_tag_t t __unused, bus_space_handle_t bsh,
+ bus_size_t offset, bus_size_t size __unused,
+ bus_space_handle_t *nbshp)
+{
+
+ *nbshp = bsh + offset;
+ return (0);
+}
+
+/*
+ * Allocate a region of memory that is accessible to devices in bus space.
+ */
+
+int bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart,
+ bus_addr_t rend, bus_size_t size, bus_size_t align,
+ bus_size_t boundary, int flags, bus_addr_t *addrp,
+ bus_space_handle_t *bshp);
+
+/*
+ * Free a region of bus space accessible memory.
+ */
+
+static __inline void bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh,
+ bus_size_t size);
+
+static __inline void
+bus_space_free(bus_space_tag_t t __unused, bus_space_handle_t bsh __unused,
+ bus_size_t size __unused)
+{
+}
+
+
+#if defined(_AMD64_BUS_PIO_H_) || defined(_AMD64_BUS_MEMIO_H_)
+
+/*
+ * Read a 1, 2, 4, or 8 byte quantity from bus space
+ * described by tag/handle/offset.
+ */
+static __inline u_int8_t bus_space_read_1(bus_space_tag_t tag,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static __inline u_int16_t bus_space_read_2(bus_space_tag_t tag,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static __inline u_int32_t bus_space_read_4(bus_space_tag_t tag,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static __inline u_int8_t
+bus_space_read_1(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+#if defined (_AMD64_BUS_PIO_H_)
+#if defined (_AMD64_BUS_MEMIO_H_)
+ if (tag == AMD64_BUS_SPACE_IO)
+#endif
+ return (inb(handle + offset));
+#endif
+#if defined (_AMD64_BUS_MEMIO_H_)
+ return (*(volatile u_int8_t *)(handle + offset));
+#endif
+}
+
+static __inline u_int16_t
+bus_space_read_2(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+#if defined(_AMD64_BUS_PIO_H_)
+#if defined(_AMD64_BUS_MEMIO_H_)
+ if (tag == AMD64_BUS_SPACE_IO)
+#endif
+ return (inw(handle + offset));
+#endif
+#if defined(_AMD64_BUS_MEMIO_H_)
+ return (*(volatile u_int16_t *)(handle + offset));
+#endif
+}
+
+static __inline u_int32_t
+bus_space_read_4(bus_space_tag_t tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+#if defined(_AMD64_BUS_PIO_H_)
+#if defined(_AMD64_BUS_MEMIO_H_)
+ if (tag == AMD64_BUS_SPACE_IO)
+#endif
+ return (inl(handle + offset));
+#endif
+#if defined(_AMD64_BUS_MEMIO_H_)
+ return (*(volatile u_int32_t *)(handle + offset));
+#endif
+}
+
+#if 0 /* Cause a link error for bus_space_read_8 */
+#define bus_space_read_8(t, h, o) !!! bus_space_read_8 unimplemented !!!
+#endif
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided.
+ */
+static __inline void bus_space_read_multi_1(bus_space_tag_t tag,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t *addr,
+ size_t count);
+
+static __inline void bus_space_read_multi_2(bus_space_tag_t tag,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t *addr,
+ size_t count);
+
+static __inline void bus_space_read_multi_4(bus_space_tag_t tag,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t *addr,
+ size_t count);
+
+static __inline void
+bus_space_read_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t *addr, size_t count)
+{
+#if defined(_AMD64_BUS_PIO_H_)
+#if defined(_AMD64_BUS_MEMIO_H_)
+ if (tag == AMD64_BUS_SPACE_IO)
+#endif
+ insb(bsh + offset, addr, count);
+#endif
+#if defined(_AMD64_BUS_MEMIO_H_)
+#if defined(_AMD64_BUS_PIO_H_)
+ else
+#endif
+ {
+#ifdef __GNUCLIKE_ASM
+ __asm __volatile(" \n\
+ cld \n\
+ 1: movb (%2),%%al \n\
+ stosb \n\
+ loop 1b" :
+ "=D" (addr), "=c" (count) :
+ "r" (bsh + offset), "0" (addr), "1" (count) :
+ "%eax", "memory");
+#endif
+ }
+#endif
+}
+
+static __inline void
+bus_space_read_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t *addr, size_t count)
+{
+#if defined(_AMD64_BUS_PIO_H_)
+#if defined(_AMD64_BUS_MEMIO_H_)
+ if (tag == AMD64_BUS_SPACE_IO)
+#endif
+ insw(bsh + offset, addr, count);
+#endif
+#if defined(_AMD64_BUS_MEMIO_H_)
+#if defined(_AMD64_BUS_PIO_H_)
+ else
+#endif
+ {
+#ifdef __GNUCLIKE_ASM
+ __asm __volatile(" \n\
+ cld \n\
+ 1: movw (%2),%%ax \n\
+ stosw \n\
+ loop 1b" :
+ "=D" (addr), "=c" (count) :
+ "r" (bsh + offset), "0" (addr), "1" (count) :
+ "%eax", "memory");
+#endif
+ }
+#endif
+}
+
+static __inline void
+bus_space_read_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t *addr, size_t count)
+{
+#if defined(_AMD64_BUS_PIO_H_)
+#if defined(_AMD64_BUS_MEMIO_H_)
+ if (tag == AMD64_BUS_SPACE_IO)
+#endif
+ insl(bsh + offset, addr, count);
+#endif
+#if defined(_AMD64_BUS_MEMIO_H_)
+#if defined(_AMD64_BUS_PIO_H_)
+ else
+#endif
+ {
+#ifdef __GNUCLIKE_ASM
+ __asm __volatile(" \n\
+ cld \n\
+ 1: movl (%2),%%eax \n\
+ stosl \n\
+ loop 1b" :
+ "=D" (addr), "=c" (count) :
+ "r" (bsh + offset), "0" (addr), "1" (count) :
+ "%eax", "memory");
+#endif
+ }
+#endif
+}
+
+#if 0 /* Cause a link error for bus_space_read_multi_8 */
+#define bus_space_read_multi_8 !!! bus_space_read_multi_8 unimplemented !!!
+#endif
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle and starting at `offset' and copy into
+ * buffer provided.
+ */
+static __inline void bus_space_read_region_1(bus_space_tag_t tag,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t *addr,
+ size_t count);
+
+static __inline void bus_space_read_region_2(bus_space_tag_t tag,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t *addr,
+ size_t count);
+
+static __inline void bus_space_read_region_4(bus_space_tag_t tag,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t *addr,
+ size_t count);
+
+
+static __inline void
+bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t *addr, size_t count)
+{
+#if defined(_AMD64_BUS_PIO_H_)
+#if defined(_AMD64_BUS_MEMIO_H_)
+ if (tag == AMD64_BUS_SPACE_IO)
+#endif
+ {
+ int _port_ = bsh + offset;
+#ifdef __GNUCLIKE_ASM
+ __asm __volatile(" \n\
+ cld \n\
+ 1: inb %w2,%%al \n\
+ stosb \n\
+ incl %2 \n\
+ loop 1b" :
+ "=D" (addr), "=c" (count), "=d" (_port_) :
+ "0" (addr), "1" (count), "2" (_port_) :
+ "%eax", "memory", "cc");
+#endif
+ }
+#endif
+#if defined(_AMD64_BUS_MEMIO_H_)
+#if defined(_AMD64_BUS_PIO_H_)
+ else
+#endif
+ {
+ bus_space_handle_t _port_ = bsh + offset;
+#ifdef __GNUCLIKE_ASM
+ __asm __volatile(" \n\
+ cld \n\
+ repne \n\
+ movsb" :
+ "=D" (addr), "=c" (count), "=S" (_port_) :
+ "0" (addr), "1" (count), "2" (_port_) :
+ "memory", "cc");
+#endif
+ }
+#endif
+}
+
+static __inline void
+bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t *addr, size_t count)
+{
+#if defined(_AMD64_BUS_PIO_H_)
+#if defined(_AMD64_BUS_MEMIO_H_)
+ if (tag == AMD64_BUS_SPACE_IO)
+#endif
+ {
+ int _port_ = bsh + offset;
+#ifdef __GNUCLIKE_ASM
+ __asm __volatile(" \n\
+ cld \n\
+ 1: inw %w2,%%ax \n\
+ stosw \n\
+ addl $2,%2 \n\
+ loop 1b" :
+ "=D" (addr), "=c" (count), "=d" (_port_) :
+ "0" (addr), "1" (count), "2" (_port_) :
+ "%eax", "memory", "cc");
+#endif
+ }
+#endif
+#if defined(_AMD64_BUS_MEMIO_H_)
+#if defined(_AMD64_BUS_PIO_H_)
+ else
+#endif
+ {
+ bus_space_handle_t _port_ = bsh + offset;
+#ifdef __GNUCLIKE_ASM
+ __asm __volatile(" \n\
+ cld \n\
+ repne \n\
+ movsw" :
+ "=D" (addr), "=c" (count), "=S" (_port_) :
+ "0" (addr), "1" (count), "2" (_port_) :
+ "memory", "cc");
+#endif
+ }
+#endif
+}
+
+static __inline void
+bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t *addr, size_t count)
+{
+#if defined(_AMD64_BUS_PIO_H_)
+#if defined(_AMD64_BUS_MEMIO_H_)
+ if (tag == AMD64_BUS_SPACE_IO)
+#endif
+ {
+ int _port_ = bsh + offset;
+#ifdef __GNUCLIKE_ASM
+ __asm __volatile(" \n\
+ cld \n\
+ 1: inl %w2,%%eax \n\
+ stosl \n\
+ addl $4,%2 \n\
+ loop 1b" :
+ "=D" (addr), "=c" (count), "=d" (_port_) :
+ "0" (addr), "1" (count), "2" (_port_) :
+ "%eax", "memory", "cc");
+#endif
+ }
+#endif
+#if defined(_AMD64_BUS_MEMIO_H_)
+#if defined(_AMD64_BUS_PIO_H_)
+ else
+#endif
+ {
+ bus_space_handle_t _port_ = bsh + offset;
+#ifdef __GNUCLIKE_ASM
+ __asm __volatile(" \n\
+ cld \n\
+ repne \n\
+ movsl" :
+ "=D" (addr), "=c" (count), "=S" (_port_) :
+ "0" (addr), "1" (count), "2" (_port_) :
+ "memory", "cc");
+#endif
+ }
+#endif
+}
+
+#if 0 /* Cause a link error for bus_space_read_region_8 */
+#define bus_space_read_region_8 !!! bus_space_read_region_8 unimplemented !!!
+#endif
+
+/*
+ * Write the 1, 2, 4, or 8 byte value `value' to bus space
+ * described by tag/handle/offset.
+ */
+
+static __inline void bus_space_write_1(bus_space_tag_t tag,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t value);
+
+static __inline void bus_space_write_2(bus_space_tag_t tag,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t value);
+
+static __inline void bus_space_write_4(bus_space_tag_t tag,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t value);
+
+static __inline void
+bus_space_write_1(bus_space_tag_t tag, bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t value)
+{
+#if defined(_AMD64_BUS_PIO_H_)
+#if defined(_AMD64_BUS_MEMIO_H_)
+ if (tag == AMD64_BUS_SPACE_IO)
+#endif
+ outb(bsh + offset, value);
+#endif
+#if defined(_AMD64_BUS_MEMIO_H_)
+#if defined(_AMD64_BUS_PIO_H_)
+ else
+#endif
+ *(volatile u_int8_t *)(bsh + offset) = value;
+#endif
+}
+
+static __inline void
+bus_space_write_2(bus_space_tag_t tag, bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t value)
+{
+#if defined(_AMD64_BUS_PIO_H_)
+#if defined(_AMD64_BUS_MEMIO_H_)
+ if (tag == AMD64_BUS_SPACE_IO)
+#endif
+ outw(bsh + offset, value);
+#endif
+#if defined(_AMD64_BUS_MEMIO_H_)
+#if defined(_AMD64_BUS_PIO_H_)
+ else
+#endif
+ *(volatile u_int16_t *)(bsh + offset) = value;
+#endif
+}
+
+static __inline void
+bus_space_write_4(bus_space_tag_t tag, bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t value)
+{
+#if defined(_AMD64_BUS_PIO_H_)
+#if defined(_AMD64_BUS_MEMIO_H_)
+ if (tag == AMD64_BUS_SPACE_IO)
+#endif
+ outl(bsh + offset, value);
+#endif
+#if defined(_AMD64_BUS_MEMIO_H_)
+#if defined(_AMD64_BUS_PIO_H_)
+ else
+#endif
+ *(volatile u_int32_t *)(bsh + offset) = value;
+#endif
+}
+
+#if 0 /* Cause a link error for bus_space_write_8 */
+#define bus_space_write_8 !!! bus_space_write_8 not implemented !!!
+#endif
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
+ * provided to bus space described by tag/handle/offset.
+ */
+
+static __inline void bus_space_write_multi_1(bus_space_tag_t tag,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int8_t *addr,
+ size_t count);
+static __inline void bus_space_write_multi_2(bus_space_tag_t tag,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int16_t *addr,
+ size_t count);
+
+static __inline void bus_space_write_multi_4(bus_space_tag_t tag,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int32_t *addr,
+ size_t count);
+
+static __inline void
+bus_space_write_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh,
+ bus_size_t offset, const u_int8_t *addr, size_t count)
>>> TRUNCATED FOR MAIL (1000 lines) <<<
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