PERFORCE change 48801 for review

[Juli Mallett]

http://perforce.freebsd.org/chv.cgi?CH=48801

Change 48801 by jmallett at jmallett_oingo on 2004/03/12 11:03:06

	submit the night's work...  add some comments...  set up
	xcontext, curious to see if that works...  panic when i don't
	mean printf...  printf when i can't live with panic, right now.

Affected files ...

.. //depot/projects/mips/sys/mips/mips/tlb.c#23 edit

Differences ...

==== //depot/projects/mips/sys/mips/mips/tlb.c#23 (text+ko) ====

@@ -59,6 +59,14 @@
 pt_entry_t *kptmap;
 vm_size_t kptsize;
 
+/*
+ * I think I want to keep a "wired" TLB map here, with space for PTEs
+ * for the whole TLB, allocated in tlb_bootstrap(), and then sourced
+ * for invalidate() operations, this has the added effect of making
+ * invalidate_all() update wired entries, without making it just avoid
+ * a part of the TLB.
+ */
+
 #ifdef notyet
 /*
  * XXX Move the ASID code here.
@@ -78,7 +86,7 @@
 	kptsize = pages;
 	kptmap = (pt_entry_t *) (*ptalloc)(kptsize * sizeof (pt_entry_t));
 
-	printf("Kernel page table maps %ld %dK pages\n", pages, PAGE_SIZE / 1024);
+	printf("Kernel page table maps %ld %dK pages and is %ldK\n", pages, PAGE_SIZE / 1024, (kptsize * sizeof (pt_entry_t)) / 1024);
 
 	/*
 	 * Set global bit on all pages.
@@ -99,6 +107,11 @@
 	 * Just one wired TLB entry.
 	 */
 	mips_wr_wired(1);
+
+	/*
+	 * Set up page table.
+	 */
+	mips_wr_xcontext((uintptr_t)kptmap);
 }
 
 void
@@ -113,7 +126,7 @@
 	if (pte_valid(pte))
 		tlb_invalidate_page(va);
 	if ((bits & PG_V) == 0)
-		printf("pmap %p entering invalid mapping for va %lx to pa %lx [%lx]\n",
+		panic("pmap %p entering invalid mapping for va %lx to pa %lx [%lx]",
 		       pmap, (u_long)va, (u_long)pa, (u_long)bits);
 	*pte &= PG_G;
 	*pte |= MIPS_PA_TO_PFN(pa) | bits;
@@ -211,6 +224,15 @@
 
 /*
  * PTE was not dirty and is being written to.  XXX kernel only for now.
+ *
+ * XXX So it looks like something is broken above, because we end up
+ * with duplicate EntryHi's in the TLB, and that's how we get here.
+ * I think maybe the TLBL/TLBS routing is wrong, but I'm not prepared
+ * to bet on that.  I will probably do a brief indirection though, and
+ * check tlbp.  I guess ideally the TLBMiss handler would be called with
+ * an Index, since we can obviously just choose a Random one, and so
+ * forth, rather than using tlbwr, that'd make overloading said handler
+ * a lot easier.  But I'm probably just a bad person.
  */
 void
 tlb_modified(void *badvaddr)
@@ -228,8 +250,10 @@
 		panic("write to invalid page");
 	if (pte_ro(pte))
 		panic("write to ro page");
-	if (pte_dirty(pte))
-		panic("dirty page caused a TLBMod");
+	if (pte_dirty(pte)) {
+		tlb_invalidate_all();
+		printf("dirty page caused a TLBMod\n");
+	}
 
 	/*
 	 * Mark the page dirty.