PERFORCE change 38170 for review
Marcel Moolenaar
marcel at FreeBSD.org
Tue Sep 16 20:27:07 PDT 2003
http://perforce.freebsd.org/chv.cgi?CH=38170
Change 38170 by marcel at marcel_nfs on 2003/09/16 20:26:15
IFC @38168
Affected files ...
.. //depot/projects/uart/boot/i386/libi386/comconsole.c#3 integrate
.. //depot/projects/uart/boot/pc98/libpc98/comconsole.c#3 integrate
.. //depot/projects/uart/dev/aac/aac.c#7 integrate
.. //depot/projects/uart/dev/ata/ata-lowlevel.c#7 integrate
.. //depot/projects/uart/dev/ata/atapi-cd.c#7 integrate
.. //depot/projects/uart/dev/ic/ns16550.h#2 integrate
.. //depot/projects/uart/dev/sio/sioreg.h#2 integrate
.. //depot/projects/uart/dev/sound/isa/mpu.c#2 integrate
.. //depot/projects/uart/dev/sound/isa/uartsio.c#2 integrate
.. //depot/projects/uart/dev/uart/uart_bus.h#29 integrate
.. //depot/projects/uart/dev/uart/uart_core.c#29 integrate
.. //depot/projects/uart/dev/uart/uart_dev_i8251.c#2 integrate
.. //depot/projects/uart/dev/uart/uart_dev_ns8250.c#29 integrate
.. //depot/projects/uart/dev/uart/uart_dev_sab82532.c#28 integrate
.. //depot/projects/uart/dev/uart/uart_dev_z8530.c#14 integrate
.. //depot/projects/uart/dev/uart/uart_if.m#11 integrate
.. //depot/projects/uart/modules/uart/Makefile#9 integrate
.. //depot/projects/uart/net/bridge.c#2 integrate
.. //depot/projects/uart/netinet/ip_dummynet.c#4 integrate
.. //depot/projects/uart/netinet/ip_fw2.c#6 integrate
.. //depot/projects/uart/pci/agp_intel.c#3 integrate
.. //depot/projects/uart/pci/if_dc.c#13 integrate
Differences ...
==== //depot/projects/uart/boot/i386/libi386/comconsole.c#3 (text+ko) ====
@@ -24,33 +24,14 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/boot/i386/libi386/comconsole.c,v 1.9 2003/08/25 23:28:31 obrien Exp $");
+__FBSDID("$FreeBSD: src/sys/boot/i386/libi386/comconsole.c,v 1.10 2003/09/16 11:24:23 bde Exp $");
#include <stand.h>
#include <bootstrap.h>
#include <machine/cpufunc.h>
+#include <dev/ic/ns16550.h>
#include "libi386.h"
-/* selected defines from ns16550.h */
-#define com_data 0 /* data register (R/W) */
-#define com_dlbl 0 /* divisor latch low (W) */
-#define com_dlbh 1 /* divisor latch high (W) */
-#define com_ier 1 /* interrupt enable (W) */
-#define com_iir 2 /* interrupt identification (R) */
-#define com_fifo 2 /* FIFO control (W) */
-#define com_lctl 3 /* line control register (R/W) */
-#define com_cfcr 3 /* line control register (R/W) */
-#define com_mcr 4 /* modem control register (R/W) */
-#define com_lsr 5 /* line status register (R/W) */
-#define com_msr 6 /* modem status register (R/W) */
-
-/* selected defines from sioreg.h */
-#define CFCR_DLAB 0x80
-#define MCR_RTS 0x02
-#define MCR_DTR 0x01
-#define LSR_TXRDY 0x20
-#define LSR_RXRDY 0x01
-
#define COMC_FMT 0x3 /* 8N1 */
#define COMC_TXWAIT 0x40000 /* transmit timeout */
#define COMC_BPS(x) (115200 / (x)) /* speed to DLAB divisor */
==== //depot/projects/uart/boot/pc98/libpc98/comconsole.c#3 (text+ko) ====
@@ -24,33 +24,14 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/boot/pc98/libpc98/comconsole.c,v 1.4 2003/09/08 09:11:20 obrien Exp $");
+__FBSDID("$FreeBSD: src/sys/boot/pc98/libpc98/comconsole.c,v 1.5 2003/09/16 11:24:23 bde Exp $");
#include <stand.h>
#include <bootstrap.h>
#include <machine/cpufunc.h>
+#include <dev/ic/ns16550.h>
#include "libi386.h"
-/* selected defines from ns16550.h */
-#define com_data 0 /* data register (R/W) */
-#define com_dlbl 0 /* divisor latch low (W) */
-#define com_dlbh 1 /* divisor latch high (W) */
-#define com_ier 1 /* interrupt enable (W) */
-#define com_iir 2 /* interrupt identification (R) */
-#define com_fifo 2 /* FIFO control (W) */
-#define com_lctl 3 /* line control register (R/W) */
-#define com_cfcr 3 /* line control register (R/W) */
-#define com_mcr 4 /* modem control register (R/W) */
-#define com_lsr 5 /* line status register (R/W) */
-#define com_msr 6 /* modem status register (R/W) */
-
-/* selected defines from sioreg.h */
-#define CFCR_DLAB 0x80
-#define MCR_RTS 0x02
-#define MCR_DTR 0x01
-#define LSR_TXRDY 0x20
-#define LSR_RXRDY 0x01
-
#define COMC_FMT 0x3 /* 8N1 */
#define COMC_TXWAIT 0x40000 /* transmit timeout */
#define COMC_BPS(x) (115200 / (x)) /* speed to DLAB divisor */
==== //depot/projects/uart/dev/aac/aac.c#7 (text+ko) ====
@@ -28,7 +28,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/dev/aac/aac.c,v 1.77 2003/09/01 20:44:18 scottl Exp $");
+__FBSDID("$FreeBSD: src/sys/dev/aac/aac.c,v 1.78 2003/09/16 16:07:15 scottl Exp $");
/*
* Driver for the Adaptec 'FSA' family of PCI/SCSI RAID adapters.
@@ -1877,7 +1877,11 @@
error = ENOENT;
goto out;
}
-
+
+ /* wrap the pi so the following test works */
+ if (pi >= aac_qinfo[queue].size)
+ pi = 0;
+
notify = 0;
if (ci == pi + 1)
notify++;
==== //depot/projects/uart/dev/ata/ata-lowlevel.c#7 (text+ko) ====
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/dev/ata/ata-lowlevel.c,v 1.11 2003/09/10 09:57:16 sos Exp $");
+__FBSDID("$FreeBSD: src/sys/dev/ata/ata-lowlevel.c,v 1.13 2003/09/16 15:21:37 sos Exp $");
#include "opt_ata.h"
#include <sys/param.h>
@@ -270,14 +270,28 @@
{
struct ata_channel *ch = (struct ata_channel *)data;
struct ata_request *request = ch->running;
- u_int8_t status;
int length;
- /* if the channel is idle this interrupt is not for us (shared) */
- if (ch->state == ATA_IDLE)
+ /* ignore this interrupt if there is no running request */
+ if (!request) {
+ if (ATA_LOCK_CH(ch, ATA_CONTROL)) {
+ u_int8_t status = ATA_IDX_INB(ch, ATA_STATUS);
+ u_int8_t error = ATA_IDX_INB(ch, ATA_ERROR);
+
+ if (bootverbose)
+ ata_printf(ch, -1,
+ "spurious interrupt - status=0x%02x error=0x%02x\n",
+ status, error);
+ ATA_UNLOCK_CH(ch);
+ }
+ else {
+ if (bootverbose)
+ ata_printf(ch, -1, "spurious interrupt - channel busy\n");
+ }
return;
+ }
- /* if device is busy it didn't interrupt, ignore interrupt (shared) */
+ /* ignore interrupt if device is busy */
if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
DELAY(100);
if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DRQ))
@@ -285,23 +299,8 @@
}
/* clear interrupt and get status */
- status = ATA_IDX_INB(ch, ATA_STATUS);
+ request->status = ATA_IDX_INB(ch, ATA_STATUS);
- /* if we dont have a running request shout and ignore this interrupt */
- if (request == NULL) {
- if (1 || bootverbose) {
- printf("ata%d: spurious interrupt - ", device_get_unit(ch->dev));
- if (request)
- printf("request OK - ");
- printf("status=0x%02x error=0x%02x reason=0x%02x\n",
- status, ATA_IDX_INB(ch, ATA_ERROR),
- ATA_IDX_INB(ch, ATA_IREASON));
- }
- return;
- }
-
- request->status = status;
-
switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
/* ATA PIO data transfer and control commands */
@@ -545,15 +544,19 @@
stat0, err, lsb, msb);
if (!(stat0 & ATA_S_BUSY)) {
if (err == ATA_E_ILI) {
- if (stat0 & ATA_S_READY) {
+ if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
+ ch->devices |= ATA_ATAPI_MASTER;
+ }
+ else if (stat0 & ATA_S_READY) {
ch->devices |= ATA_ATA_MASTER;
}
- else if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
- ch->devices |= ATA_ATAPI_MASTER;
- }
+ }
+ else if (err == lsb && err == msb) {
+ ATA_IDX_OUTB(ch, ATA_ERROR, 0xff);
+ DELAY(10);
+ if (stat0 == ATA_IDX_INB(ch, ATA_STATUS))
+ stat0 |= ATA_S_BUSY;
}
- else if (err == lsb && err == msb)
- stat0 |= ATA_S_BUSY;
}
}
if (stat1 & ATA_S_BUSY) {
@@ -569,15 +572,19 @@
stat1, err, lsb, msb);
if (!(stat1 & ATA_S_BUSY)) {
if (err == ATA_E_ILI) {
- if (stat1 & ATA_S_READY) {
+ if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
+ ch->devices |= ATA_ATAPI_SLAVE;
+ }
+ else if (stat1 & ATA_S_READY) {
ch->devices |= ATA_ATA_SLAVE;
}
- else if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
- ch->devices |= ATA_ATAPI_SLAVE;
- }
+ }
+ else if (err == lsb && err == msb) {
+ ATA_IDX_OUTB(ch, ATA_ERROR, 0xff);
+ DELAY(10);
+ if (stat1 == ATA_IDX_INB(ch, ATA_STATUS))
+ stat1 |= ATA_S_BUSY;
}
- else if (err == lsb && err == msb)
- stat1 |= ATA_S_BUSY;
}
}
if (mask == 0x01) /* wait for master only */
==== //depot/projects/uart/dev/ata/atapi-cd.c#7 (text+ko) ====
@@ -27,7 +27,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/dev/ata/atapi-cd.c,v 1.144 2003/09/11 19:27:24 phk Exp $");
+__FBSDID("$FreeBSD: src/sys/dev/ata/atapi-cd.c,v 1.145 2003/09/16 14:41:44 sos Exp $");
#include "opt_ata.h"
#include <sys/param.h>
@@ -1034,7 +1034,7 @@
break;
case DIOCGMEDIASIZE:
- *(off_t *)addr = cdp->disk_size * cdp->block_size;
+ *(off_t *)addr = (off_t)cdp->disk_size * (off_t)cdp->block_size;
break;
case DIOCGSECTORSIZE:
==== //depot/projects/uart/dev/ic/ns16550.h#2 (text+ko) ====
@@ -31,21 +31,165 @@
* SUCH DAMAGE.
*
* from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91
- * $FreeBSD: src/sys/dev/ic/ns16550.h,v 1.9 2002/09/22 08:51:28 phk Exp $
+ * $FreeBSD: src/sys/dev/ic/ns16550.h,v 1.14 2003/09/16 14:21:17 bde Exp $
*/
/*
- * NS16550 UART registers
+ * NS8250... UART registers.
*/
+
+/* 8250 registers #[0-6]. */
+
#define com_data 0 /* data register (R/W) */
-#define com_dlbl 0 /* divisor latch low (W) */
-#define com_dlbh 1 /* divisor latch high (W) */
-#define com_ier 1 /* interrupt enable (W) */
-#define com_iir 2 /* interrupt identification (R) */
-#define com_fifo 2 /* FIFO control (W) */
-#define com_lctl 3 /* line control register (R/W) */
-#define com_cfcr 3 /* line control register (R/W) */
+#define com_thr com_data /* transmitter holding register (W) */
+#define com_rhr com_data /* receiver holding register (R) */
+
+#define com_ier 1 /* interrupt enable register (W) */
+#define IER_ERXRDY 0x1
+#define IER_ETXRDY 0x2
+#define IER_ERLS 0x4
+#define IER_EMSC 0x8
+
+#define com_iir 2 /* interrupt identification register (R) */
+#define com_isr com_iir /* interrupt status register (R) */
+#define IIR_IMASK 0xf
+#define IIR_RXTOUT 0xc
+#define IIR_RLS 0x6
+#define IIR_RXRDY 0x4
+#define IIR_TXRDY 0x2
+#define IIR_NOPEND 0x1
+#define IIR_MLSC 0x0
+#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
+
+#define com_lcr 3 /* line control register (R/W) */
+#define com_lctl com_lcr
+#define com_cfcr com_lcr /* character format control register (R/W) */
+#define LCR_DLAB 0x80
+#define CFCR_DLAB LCR_DLAB
+#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
+#define CFCR_EFR_ENABLE LCR_EFR_ENABLE
+#define CFCR_SBREAK 0x40
+#define CFCR_PZERO 0x30
+#define CFCR_PONE 0x20
+#define CFCR_PEVEN 0x10
+#define CFCR_PODD 0x00
+#define CFCR_PENAB 0x08
+#define CFCR_STOPB 0x04
+#define CFCR_8BITS 0x03
+#define CFCR_7BITS 0x02
+#define CFCR_6BITS 0x01
+#define CFCR_5BITS 0x00
+
#define com_mcr 4 /* modem control register (R/W) */
+#define MCR_PRESCALE 0x80 /* only available on 16650 up */
+#define MCR_LOOPBACK 0x10
+#define MCR_IENABLE 0x08
+#define MCR_DRS 0x04
+#define MCR_RTS 0x02
+#define MCR_DTR 0x01
+
#define com_lsr 5 /* line status register (R/W) */
+#define LSR_RCV_FIFO 0x80
+#define LSR_TSRE 0x40
+#define LSR_TXRDY 0x20
+#define LSR_BI 0x10
+#define LSR_FE 0x08
+#define LSR_PE 0x04
+#define LSR_OE 0x02
+#define LSR_RXRDY 0x01
+#define LSR_RCV_MASK 0x1f
+
#define com_msr 6 /* modem status register (R/W) */
-#define com_scr 7 /* scratch register for 16450 up (R/W) */
+#define MSR_DCD 0x80
+#define MSR_RI 0x40
+#define MSR_DSR 0x20
+#define MSR_CTS 0x10
+#define MSR_DDCD 0x08
+#define MSR_TERI 0x04
+#define MSR_DDSR 0x02
+#define MSR_DCTS 0x01
+
+/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */
+#define com_dll 0 /* divisor latch low (R/W) */
+#define com_dlbl com_dll
+#define com_dlm 1 /* divisor latch high (R/W) */
+#define com_dlbh com_dlm
+
+/* 16450 register #7. Not multiplexed. */
+#define com_scr 7 /* scratch register (R/W) */
+
+/* 16550 register #2. Not multiplexed. */
+#define com_fcr 2 /* FIFO control register (W) */
+#define com_fifo com_fcr
+#define FIFO_ENABLE 0x01
+#define FIFO_RCV_RST 0x02
+#define FIFO_XMT_RST 0x04
+#define FIFO_DMA_MODE 0x08
+#define FIFO_RX_LOW 0x00
+#define FIFO_RX_MEDL 0x40
+#define FIFO_RX_MEDH 0x80
+#define FIFO_RX_HIGH 0xc0
+
+/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */
+
+#define com_efr 2 /* enhanced features register (R/W) */
+#define EFR_AUTOCTS 0x80
+#define EFR_AUTORTS 0x40
+#define EFR_EFE 0x10 /* enhanced functions enable */
+
+#define com_xon1 4 /* XON 1 character (R/W) */
+#define com_xon2 5 /* XON 2 character (R/W) */
+#define com_xoff1 6 /* XOFF 1 character (R/W) */
+#define com_xoff2 7 /* XOFF 2 character (R/W) */
+
+/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */
+#define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */
+
+/* 16950 register #3. R/W access enabled by ACR[7]. */
+#define com_rfl 3 /* receiver fifo level (R) */
+
+/*
+ * 16950 register #4. Access enabled by ACR[7]. Also requires
+ * !LCR_EFR_ENABLE.
+ */
+#define com_tfl 4 /* transmitter fifo level (R) */
+
+/*
+ * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also
+ * requires ACR[6].
+ */
+#define com_icr 5 /* index control register (R/W) */
+
+/*
+ * 16950 register #7. It is the same as com_scr except it has a different
+ * abbreviation in the manufacturer's data sheet and it also serves as an
+ * index into the Indexed Control register set.
+ */
+#define com_spr com_scr /* scratch pad (and index) register (R/W) */
+
+/*
+ * 16950 indexed control registers #[0-0x13]. Access is via index in SPR,
+ * data in ICR (if ICR is accessible).
+ */
+
+#define com_acr 0 /* additional control register (R/W) */
+#define ACR_ASE 0x80 /* ASR/RFL/TFL enable */
+#define ACR_ICRE 0x40 /* ICR enable */
+#define ACR_TLE 0x20 /* TTL/RTL enable */
+
+#define com_cpr 1 /* clock prescaler register (R/W) */
+#define com_tcr 2 /* times clock register (R/W) */
+#define com_ttl 4 /* transmitter trigger level (R/W) */
+#define com_rtl 5 /* receiver trigger level (R/W) */
+/* ... */
+
+#ifdef PC98
+/* Hardware extension mode register for RSB-2000/3000. */
+#define com_emr com_msr
+#define EMR_EXBUFF 0x04
+#define EMR_CTSFLW 0x08
+#define EMR_DSRFLW 0x10
+#define EMR_RTSFLW 0x20
+#define EMR_DTRFLW 0x40
+#define EMR_EFMODE 0x80
+#endif
==== //depot/projects/uart/dev/sio/sioreg.h#2 (text+ko) ====
@@ -31,97 +31,12 @@
* SUCH DAMAGE.
*
* from: @(#)comreg.h 7.2 (Berkeley) 5/9/91
- * $FreeBSD: src/sys/dev/sio/sioreg.h,v 1.22 2003/03/18 21:26:28 sobomax Exp $
+ * $FreeBSD: src/sys/dev/sio/sioreg.h,v 1.23 2003/09/16 08:08:08 bde Exp $
*/
/* Receiver clock frequency for "standard" pc serial ports. */
#define DEFAULT_RCLK 1843200
-/* interrupt enable register */
-#define IER_ERXRDY 0x1
-#define IER_ETXRDY 0x2
-#define IER_ERLS 0x4
-#define IER_EMSC 0x8
-
-/* interrupt identification register */
-#define IIR_IMASK 0xf
-#define IIR_RXTOUT 0xc
-#define IIR_RLS 0x6
-#define IIR_RXRDY 0x4
-#define IIR_TXRDY 0x2
-#define IIR_NOPEND 0x1
-#define IIR_MLSC 0x0
-#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
-
-/* fifo control register */
-#define FIFO_ENABLE 0x01
-#define FIFO_RCV_RST 0x02
-#define FIFO_XMT_RST 0x04
-#define FIFO_DMA_MODE 0x08
-#define FIFO_RX_LOW 0x00
-#define FIFO_RX_MEDL 0x40
-#define FIFO_RX_MEDH 0x80
-#define FIFO_RX_HIGH 0xc0
-
-/* character format control register (aka line control register) */
-#define CFCR_DLAB 0x80
-#define CFCR_SBREAK 0x40
-#define CFCR_PZERO 0x30
-#define CFCR_PONE 0x20
-#define CFCR_PEVEN 0x10
-#define CFCR_PODD 0x00
-#define CFCR_PENAB 0x08
-#define CFCR_STOPB 0x04
-#define CFCR_8BITS 0x03
-#define CFCR_7BITS 0x02
-#define CFCR_6BITS 0x01
-#define CFCR_5BITS 0x00
-#define CFCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
-
-/* modem control register */
-#define MCR_PRESCALE 0x80 /* only available on 16650 up */
-#define MCR_LOOPBACK 0x10
-#define MCR_IENABLE 0x08
-#define MCR_DRS 0x04
-#define MCR_RTS 0x02
-#define MCR_DTR 0x01
-
-/* line status register */
-#define LSR_RCV_FIFO 0x80
-#define LSR_TSRE 0x40
-#define LSR_TXRDY 0x20
-#define LSR_BI 0x10
-#define LSR_FE 0x08
-#define LSR_PE 0x04
-#define LSR_OE 0x02
-#define LSR_RXRDY 0x01
-#define LSR_RCV_MASK 0x1f
-
-/* modem status register */
-#define MSR_DCD 0x80
-#define MSR_RI 0x40
-#define MSR_DSR 0x20
-#define MSR_CTS 0x10
-#define MSR_DDCD 0x08
-#define MSR_TERI 0x04
-#define MSR_DDSR 0x02
-#define MSR_DCTS 0x01
-
-/* enhanced feature register (only available on 16650 up) */
-#define com_efr com_fifo
-#define EFR_EFE 0x10 /* enhanced functions enable */
-
-#ifdef PC98
-/* Hardware extension mode register for RSB-2000/3000. */
-#define com_emr com_msr
-#define EMR_EXBUFF 0x04
-#define EMR_CTSFLW 0x08
-#define EMR_DSRFLW 0x10
-#define EMR_RTSFLW 0x20
-#define EMR_DTRFLW 0x40
-#define EMR_EFMODE 0x80
-#endif
-
/* speed to initialize to during chip tests */
#define SIO_TEST_SPEED 9600
==== //depot/projects/uart/dev/sound/isa/mpu.c#2 (text+ko) ====
@@ -33,7 +33,7 @@
* This handles io against /dev/midi, the midi {in, out}put event queues
* and the event/message transmittion to/from an MPU401 interface.
*
- * $FreeBSD: src/sys/dev/sound/isa/mpu.c,v 1.16 2002/04/04 21:03:16 jhb Exp $
+ * $FreeBSD: src/sys/dev/sound/isa/mpu.c,v 1.17 2003/09/16 11:04:22 bde Exp $
*
*/
@@ -42,7 +42,6 @@
#include <machine/cpufunc.h>
#include <isa/isavar.h>
-#include <dev/sio/sioreg.h>
#include <dev/ic/ns16550.h>
static devclass_t midi_devclass;
==== //depot/projects/uart/dev/sound/isa/uartsio.c#2 (text+ko) ====
@@ -42,11 +42,10 @@
* This handles io against /dev/midi, the midi {in, out}put event queues
* and the event/message transmittion to/from a serial port interface.
*
- * $FreeBSD: src/sys/dev/sound/isa/uartsio.c,v 1.13 2002/12/18 22:53:23 semenu Exp $
+ * $FreeBSD: src/sys/dev/sound/isa/uartsio.c,v 1.15 2003/09/17 01:09:10 bde Exp $
*
*/
-#include <dev/sio/sioreg.h>
#include <dev/ic/ns16550.h>
#include <dev/sound/midi/midi.h>
==== //depot/projects/uart/dev/uart/uart_bus.h#29 (text+ko) ====
@@ -23,7 +23,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * $FreeBSD: src/sys/dev/uart/uart_bus.h,v 1.2 2003/09/11 23:06:42 marcel Exp $
+ * $FreeBSD: src/sys/dev/uart/uart_bus.h,v 1.3 2003/09/17 01:41:21 marcel Exp $
*/
#ifndef _DEV_UART_BUS_H_
@@ -113,6 +113,8 @@
struct uart_bas sc_bas;
device_t sc_dev;
+ struct mtx sc_hwmtx; /* Spinlock protecting hardware. */
+
struct resource *sc_rres; /* Register resource. */
int sc_rrid;
int sc_rtype; /* SYS_RES_{IOPORT|MEMORY}. */
==== //depot/projects/uart/dev/uart/uart_core.c#29 (text+ko) ====
@@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/dev/uart/uart_core.c,v 1.2 2003/09/11 23:06:42 marcel Exp $");
+__FBSDID("$FreeBSD: src/sys/dev/uart/uart_core.c,v 1.4 2003/09/17 03:11:32 marcel Exp $");
#ifndef KLD_MODULE
#include "opt_comconsole.h"
@@ -200,17 +200,21 @@
if (sc->sc_leaving)
return;
- ipend = UART_IPEND(sc);
- if (ipend & UART_IPEND_OVERRUN)
- uart_intr_overrun(sc);
- if (ipend & UART_IPEND_BREAK)
- uart_intr_break(sc);
- if (ipend & UART_IPEND_RXREADY)
- uart_intr_rxready(sc);
- if (ipend & UART_IPEND_SIGCHG)
- uart_intr_sigchg(sc);
- if (ipend & UART_IPEND_TXIDLE)
- uart_intr_txidle(sc);
+ do {
+ ipend = UART_IPEND(sc);
+ if (ipend == 0)
+ break;
+ if (ipend & UART_IPEND_OVERRUN)
+ uart_intr_overrun(sc);
+ if (ipend & UART_IPEND_BREAK)
+ uart_intr_break(sc);
+ if (ipend & UART_IPEND_RXREADY)
+ uart_intr_rxready(sc);
+ if (ipend & UART_IPEND_SIGCHG)
+ uart_intr_sigchg(sc);
+ if (ipend & UART_IPEND_TXIDLE)
+ uart_intr_txidle(sc);
+ } while (1);
if (sc->sc_opened && sc->sc_ttypend != 0)
swi_sched(sc->sc_softih, 0);
@@ -309,6 +313,8 @@
*/
sc->sc_leaving = 1;
+ mtx_init(&sc->sc_hwmtx, "uart_hwmtx", NULL, MTX_SPIN);
+
/*
* Re-allocate. We expect that the softc contains the information
* collected by uart_bus_probe() intact.
==== //depot/projects/uart/dev/uart/uart_dev_i8251.c#2 (text+ko) ====
@@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/dev/uart/uart_dev_i8251.c,v 1.1 2003/09/07 04:59:15 imp Exp $");
+__FBSDID("$FreeBSD: src/sys/dev/uart/uart_dev_i8251.c,v 1.3 2003/09/17 03:11:32 marcel Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -427,15 +427,19 @@
{
struct i8251_softc *i8251 = (struct i8251_softc*)sc;
struct uart_bas *bas;
+ int error;
bas = &sc->sc_bas;
+ mtx_lock_spin(&sc->sc_hwmtx);
if (sc->sc_hasfifo) {
i8251_flush(bas, what);
uart_setreg(bas, REG_FCR, i8251->fcr);
uart_barrier(bas);
- return (0);
- }
- return (i8251_drain(bas, what));
+ error = 0;
+ } else
+ error = i8251_drain(bas, what);
+ mtx_unlock_spin(&sc->sc_hwmtx);
+ return (error);
}
static int
@@ -447,7 +451,9 @@
do {
old = sc->sc_hwsig;
sig = old;
+ mtx_lock_spin(&sc->sc_hwmtx);
msr = uart_getreg(&sc->sc_bas, REG_MSR);
+ mtx_unlock_spin(&sc->sc_hwmtx);
SIGCHG(msr & MSR_DSR, sig, UART_SIG_DSR, UART_SIG_DDSR);
SIGCHG(msr & MSR_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS);
SIGCHG(msr & MSR_DCD, sig, UART_SIG_DCD, UART_SIG_DDCD);
@@ -461,9 +467,12 @@
i8251_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
{
struct uart_bas *bas;
+ int error;
uint8_t lcr;
bas = &sc->sc_bas;
+ error = 0;
+ mtx_lock_spin(&sc->sc_hwmtx);
switch (request) {
case UART_IOCTL_BREAK:
lcr = uart_getreg(bas, REG_LCR);
@@ -475,9 +484,11 @@
uart_barrier(bas);
break;
default:
- return (EINVAL);
+ error = EINVAL;
+ break;
}
- return (0);
+ mtx_unlock_spin(&sc->sc_hwmtx);
+ return (error);
}
static int
@@ -488,13 +499,16 @@
uint8_t iir, lsr;
bas = &sc->sc_bas;
+ mtx_lock_spin(&sc->sc_hwmtx);
iir = uart_getreg(bas, REG_IIR);
- if (iir & IIR_NOPEND)
+ if (iir & IIR_NOPEND) {
+ mtx_unlock_spin(&sc->sc_hwmtx);
return (0);
-
+ }
ipend = 0;
if (iir & IIR_RXRDY) {
lsr = uart_getreg(bas, REG_LSR);
+ mtx_unlock_spin(&sc->sc_hwmtx);
if (lsr & LSR_OE)
ipend |= UART_IPEND_OVERRUN;
if (lsr & LSR_BI)
@@ -502,12 +516,12 @@
if (lsr & LSR_RXRDY)
ipend |= UART_IPEND_RXREADY;
} else {
+ mtx_unlock_spin(&sc->sc_hwmtx);
if (iir & IIR_TXRDY)
ipend |= UART_IPEND_TXIDLE;
else
ipend |= UART_IPEND_SIGCHG;
}
-
return ((sc->sc_leaving) ? 0 : ipend);
}
@@ -516,9 +530,13 @@
int stopbits, int parity)
{
struct uart_bas *bas;
+ int error;
bas = &sc->sc_bas;
- return (i8251_param(bas, baudrate, databits, stopbits, parity));
+ mtx_lock_spin(&sc->sc_hwmtx);
+ error = i8251_param(bas, baudrate, databits, stopbits, parity);
+ mtx_unlock_spin(&sc->sc_hwmtx);
+ return (error);
}
static int
@@ -661,17 +679,28 @@
uint8_t lsr;
bas = &sc->sc_bas;
- while (!uart_rx_full(sc)) {
- lsr = uart_getreg(bas, REG_LSR);
- if ((lsr & LSR_RXRDY) == 0)
+ mtx_lock_spin(&sc->sc_hwmtx);
+ lsr = uart_getreg(bas, REG_LSR);
+ while (lsr & LSR_RXRDY) {
+ if (uart_rx_full(sc)) {
+ sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
break;
+ }
xc = uart_getreg(bas, REG_DATA);
if (lsr & LSR_FE)
xc |= UART_STAT_FRAMERR;
if (lsr & LSR_PE)
xc |= UART_STAT_PARERR;
uart_rx_put(sc, xc);
+ lsr = uart_getreg(bas, REG_LSR);
+ }
+ /* Discard everything left in the Rx FIFO. */
+ while (lsr & LSR_RXRDY) {
+ (void)uart_getreg(bas, REG_DATA);
+ uart_barrier(bas);
+ lsr = uart_getreg(bas, REG_LSR);
}
+ mtx_unlock_spin(&sc->sc_hwmtx);
return (0);
}
@@ -695,6 +724,7 @@
UART_SIG_DRTS);
}
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
+ mtx_lock_spin(&sc->sc_hwmtx);
i8251->mcr &= ~(MCR_DTR|MCR_RTS);
if (new & UART_SIG_DTR)
i8251->mcr |= MCR_DTR;
@@ -702,6 +732,7 @@
i8251->mcr |= MCR_RTS;
uart_setreg(bas, REG_MCR, i8251->mcr);
uart_barrier(bas);
+ mtx_unlock_spin(&sc->sc_hwmtx);
return (0);
}
@@ -713,6 +744,7 @@
int i;
bas = &sc->sc_bas;
+ mtx_lock_spin(&sc->sc_hwmtx);
while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
;
uart_setreg(bas, REG_IER, i8251->ier | IER_ETXRDY);
@@ -722,5 +754,6 @@
uart_barrier(bas);
}
sc->sc_txbusy = 1;
+ mtx_unlock_spin(&sc->sc_hwmtx);
return (0);
}
==== //depot/projects/uart/dev/uart/uart_dev_ns8250.c#29 (text+ko) ====
@@ -25,7 +25,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/dev/uart/uart_dev_ns8250.c,v 1.3 2003/09/13 06:25:04 marcel Exp $");
+__FBSDID("$FreeBSD: src/sys/dev/uart/uart_dev_ns8250.c,v 1.5 2003/09/17 03:11:32 marcel Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -427,15 +427,19 @@
{
struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
struct uart_bas *bas;
+ int error;
bas = &sc->sc_bas;
+ mtx_lock_spin(&sc->sc_hwmtx);
if (sc->sc_hasfifo) {
ns8250_flush(bas, what);
uart_setreg(bas, REG_FCR, ns8250->fcr);
uart_barrier(bas);
- return (0);
- }
- return (ns8250_drain(bas, what));
+ error = 0;
+ } else
+ error = ns8250_drain(bas, what);
+ mtx_unlock_spin(&sc->sc_hwmtx);
+ return (error);
}
static int
@@ -447,7 +451,9 @@
do {
old = sc->sc_hwsig;
sig = old;
+ mtx_lock_spin(&sc->sc_hwmtx);
msr = uart_getreg(&sc->sc_bas, REG_MSR);
+ mtx_unlock_spin(&sc->sc_hwmtx);
SIGCHG(msr & MSR_DSR, sig, UART_SIG_DSR, UART_SIG_DDSR);
SIGCHG(msr & MSR_CTS, sig, UART_SIG_CTS, UART_SIG_DCTS);
SIGCHG(msr & MSR_DCD, sig, UART_SIG_DCD, UART_SIG_DDCD);
@@ -461,9 +467,12 @@
ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
{
struct uart_bas *bas;
+ int error;
uint8_t efr, lcr;
bas = &sc->sc_bas;
+ error = 0;
+ mtx_lock_spin(&sc->sc_hwmtx);
switch (request) {
case UART_IOCTL_BREAK:
lcr = uart_getreg(bas, REG_LCR);
@@ -505,9 +514,11 @@
uart_barrier(bas);
break;
default:
- return (EINVAL);
+ error = EINVAL;
+ break;
}
- return (0);
+ mtx_unlock_spin(&sc->sc_hwmtx);
+ return (error);
}
static int
@@ -518,13 +529,16 @@
uint8_t iir, lsr;
bas = &sc->sc_bas;
+ mtx_lock_spin(&sc->sc_hwmtx);
iir = uart_getreg(bas, REG_IIR);
- if (iir & IIR_NOPEND)
+ if (iir & IIR_NOPEND) {
+ mtx_unlock_spin(&sc->sc_hwmtx);
return (0);
-
+ }
ipend = 0;
if (iir & IIR_RXRDY) {
lsr = uart_getreg(bas, REG_LSR);
+ mtx_unlock_spin(&sc->sc_hwmtx);
if (lsr & LSR_OE)
ipend |= UART_IPEND_OVERRUN;
if (lsr & LSR_BI)
@@ -532,12 +546,12 @@
if (lsr & LSR_RXRDY)
ipend |= UART_IPEND_RXREADY;
} else {
+ mtx_unlock_spin(&sc->sc_hwmtx);
if (iir & IIR_TXRDY)
ipend |= UART_IPEND_TXIDLE;
else
ipend |= UART_IPEND_SIGCHG;
}
-
return ((sc->sc_leaving) ? 0 : ipend);
}
@@ -546,9 +560,13 @@
int stopbits, int parity)
{
struct uart_bas *bas;
+ int error;
bas = &sc->sc_bas;
- return (ns8250_param(bas, baudrate, databits, stopbits, parity));
+ mtx_lock_spin(&sc->sc_hwmtx);
+ error = ns8250_param(bas, baudrate, databits, stopbits, parity);
+ mtx_unlock_spin(&sc->sc_hwmtx);
+ return (error);
}
static int
@@ -697,17 +715,28 @@
uint8_t lsr;
bas = &sc->sc_bas;
- while (!uart_rx_full(sc)) {
- lsr = uart_getreg(bas, REG_LSR);
- if ((lsr & LSR_RXRDY) == 0)
+ mtx_lock_spin(&sc->sc_hwmtx);
+ lsr = uart_getreg(bas, REG_LSR);
+ while (lsr & LSR_RXRDY) {
+ if (uart_rx_full(sc)) {
+ sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
break;
+ }
xc = uart_getreg(bas, REG_DATA);
if (lsr & LSR_FE)
xc |= UART_STAT_FRAMERR;
if (lsr & LSR_PE)
xc |= UART_STAT_PARERR;
uart_rx_put(sc, xc);
+ lsr = uart_getreg(bas, REG_LSR);
+ }
+ /* Discard everything left in the Rx FIFO. */
+ while (lsr & LSR_RXRDY) {
+ (void)uart_getreg(bas, REG_DATA);
+ uart_barrier(bas);
+ lsr = uart_getreg(bas, REG_LSR);
}
+ mtx_unlock_spin(&sc->sc_hwmtx);
>>> TRUNCATED FOR MAIL (1000 lines) <<<
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