PERFORCE change 42112 for review
Juli Mallett
jmallett at FreeBSD.org
Wed Nov 12 00:29:52 PST 2003
http://perforce.freebsd.org/chv.cgi?CH=42112
Change 42112 by jmallett at jmallett_dalek on 2003/11/12 00:28:53
Nuke some redundency, clean up flags a little, lots of code still
could use a re-work for clarity. Tons. Print the current process.
Re-organize some vector init code. Get rid of some layering badness
with regard to touching the TLB, etc.
Affected files ...
.. //depot/projects/mips/sys/mips/include/cpuregs.h#14 edit
.. //depot/projects/mips/sys/mips/mips/cache.c#6 edit
.. //depot/projects/mips/sys/mips/mips/cache_mipsNN.c#2 edit
.. //depot/projects/mips/sys/mips/mips/cache_r5k_subr.S#3 edit
.. //depot/projects/mips/sys/mips/mips/locore.S#9 edit
.. //depot/projects/mips/sys/mips/mips/machdep.c#39 edit
.. //depot/projects/mips/sys/mips/mips/tlb.c#16 edit
.. //depot/projects/mips/sys/mips/mips/trap.c#14 edit
.. //depot/projects/mips/sys/mips/sgimips/ip22_cache.S#2 edit
Differences ...
==== //depot/projects/mips/sys/mips/include/cpuregs.h#14 (text+ko) ====
@@ -95,7 +95,7 @@
#define MIPS_PHYS_TO_KSEG1(x) ((vm_offset_t)(x) | MIPS_KSEG1_START)
/* Map virtual address to index in mips3 r4k virtually-indexed cache */
-#define MIPS3_VA_TO_CINDEX(x) \
+#define MIPS_VA_TO_CINDEX(x) \
((vm_offset_t)(x) & 0xffffff | MIPS_KSEG0_START)
#define MIPS_PHYS_TO_XKPHYS(cca,x) \
@@ -121,7 +121,7 @@
*/
#define MIPS_CR_BR_DELAY 0x80000000
#define MIPS_CR_COP_ERR 0x30000000
-#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
+#define MIPS_CR_EXC_CODE 0x0000007C /* five bits */
#define MIPS_CR_IP 0x0000FF00
#define MIPS_CR_EXC_CODE_SHIFT 2
@@ -154,10 +154,7 @@
/* r4k and r3k differences, see below */
#define MIPS_SR_INT_IE MIPS_SR_IE
-/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
-/*#define MIPS_SR_INT_MASK 0x0000ff00*/
-
/*
* The R2000/R3000-specific status register bit definitions.
* all bits are active when set to 1.
@@ -179,59 +176,42 @@
* R4000 status register bit definitons,
* where different from r2000/r3000.
*/
-#define MIPS3_SR_XX 0x80000000
-#define MIPS3_SR_RP 0x08000000
-#define MIPS3_SR_FR_32 0x04000000
-#define MIPS3_SR_RE 0x02000000
+#define MIPS_SR_XX 0x80000000
+#define MIPS_SR_RP 0x08000000
+#define MIPS_SR_FR_32 0x04000000
+#define MIPS_SR_RE 0x02000000
-#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
-#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
-#define MIPS3_SR_SR 0x00100000
-#define MIPS3_SR_EIE 0x00100000 /* TX79/R5900 */
-#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */
-#define MIPS3_SR_DIAG_CH 0x00040000
-#define MIPS3_SR_DIAG_CE 0x00020000
-#define MIPS3_SR_DIAG_PE 0x00010000
-#define MIPS3_SR_KX 0x00000080
-#define MIPS3_SR_SX 0x00000040
-#define MIPS3_SR_UX 0x00000020
-#define MIPS3_SR_KSU_MASK 0x00000018
-#define MIPS3_SR_KSU_USER 0x00000010
-#define MIPS3_SR_KSU_SUPER 0x00000008
-#define MIPS3_SR_KSU_KERNEL 0x00000000
-#define MIPS3_SR_ERL 0x00000004
-#define MIPS3_SR_EXL 0x00000002
-#define MIPS3_SR_IE 0x00000001
+#define MIPS_SR_DIAG_DL 0x01000000 /* QED 52xx */
+#define MIPS_SR_DIAG_IL 0x00800000 /* QED 52xx */
+#define MIPS_SR_SR 0x00100000
+#define MIPS_SR_EIE 0x00100000 /* TX79/R5900 */
+#define MIPS_SR_NMI 0x00080000 /* MIPS32/64 */
+#define MIPS_SR_DIAG_CH 0x00040000
+#define MIPS_SR_DIAG_CE 0x00020000
+#define MIPS_SR_DIAG_PE 0x00010000
+#define MIPS_SR_KX 0x00000080
+#define MIPS_SR_SX 0x00000040
+#define MIPS_SR_UX 0x00000020
+#define MIPS_SR_KSU_MASK 0x00000018
+#define MIPS_SR_KSU_USER 0x00000010
+#define MIPS_SR_KSU_SUPER 0x00000008
+#define MIPS_SR_KSU_KERNEL 0x00000000
+#define MIPS_SR_ERL 0x00000004
+#define MIPS_SR_EXL 0x00000002
+#define MIPS_SR_IE 0x00000001
-#define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
-#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
-#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
-#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
-#define MIPS_SR_KX MIPS3_SR_KX
-#define MIPS_SR_SX MIPS3_SR_SX
-#define MIPS_SR_UX MIPS3_SR_UX
-
-#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
-#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
-#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
-#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
-#define MIPS_SR_ERL MIPS3_SR_ERL
-#define MIPS_SR_EXL MIPS3_SR_EXL
-#define MIPS_SR_IE MIPS3_SR_IE
-
-
/*
* The interrupt masks.
* If a bit in the mask is 1 then the interrupt is enabled (or pending).
*/
-#define MIPS_INT_MASK 0xff00
+#define MIPS_INT_MASKX 0xff00
#define MIPS_INT_MASK_5 0x8000
#define MIPS_INT_MASK_4 0x4000
#define MIPS_INT_MASK_3 0x2000
#define MIPS_INT_MASK_2 0x1000
#define MIPS_INT_MASK_1 0x0800
#define MIPS_INT_MASK_0 0x0400
-#define MIPS_HARD_INT_MASK 0xfc00
+#define MIPS_HARD_INT_MASKX 0xfc00
#define MIPS_SOFT_INT_MASK_1 0x0200
#define MIPS_SOFT_INT_MASK_0 0x0100
@@ -239,12 +219,12 @@
* mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
* choose to enable this interrupt.
*/
-#if defined(MIPS3_ENABLE_CLOCK_INTR)
-#define MIPS3_INT_MASK MIPS_INT_MASK
-#define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK
+#if defined(MIPS_ENABLE_CLOCK_INTR)
+#define MIPS_INT_MASK MIPS_INT_MASKX
+#define MIPS_HARD_INT_MASK MIPS_HARD_INT_MASKX
#else
-#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
-#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
+#define MIPS_INT_MASK (MIPS_INT_MASKX & ~MIPS_INT_MASK_5)
+#define MIPS_HARD_INT_MASK (MIPS_HARD_INT_MASKX & ~MIPS_INT_MASK_5)
#endif
/*
@@ -253,8 +233,8 @@
* XXX XContext
*/
-#define MIPS3_CNTXT_PTE_BASE 0xFF800000
-#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
+#define MIPS_CNTXT_PTE_BASE 0xFF800000
+#define MIPS_CNTXT_BAD_VPN2 0x007FFFF0
/*
* The bits in the MIPS3 config register.
@@ -262,73 +242,73 @@
* bit 0..5: R/W, Bit 6..31: R/O
*/
-/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
-#define MIPS3_CONFIG_K0_MASK 0x00000007
+/* kseg0 coherency algorithm - see MIPS_TLB_ATTR values */
+#define MIPS_CONFIG_K0_MASK 0x00000007
/*
* R/W Update on Store Conditional
* 0: Store Conditional uses coherency algorithm specified by TLB
* 1: Store Conditional uses cacheable coherent update on write
*/
-#define MIPS3_CONFIG_CU 0x00000008
+#define MIPS_CONFIG_CU 0x00000008
-#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
-#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
-#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
+#define MIPS_CONFIG_DB 0x00000010 /* Primary D-cache line size */
+#define MIPS_CONFIG_IB 0x00000020 /* Primary I-cache line size */
+#define MIPS_CONFIG_CACHE_L1_LSIZE(config, bit) \
(((config) & (bit)) ? 32 : 16)
-#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
-#define MIPS3_CONFIG_DC_SHIFT 6
-#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
-#define MIPS3_CONFIG_IC_SHIFT 9
-#define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
-#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
+#define MIPS_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
+#define MIPS_CONFIG_DC_SHIFT 6
+#define MIPS_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
+#define MIPS_CONFIG_IC_SHIFT 9
+#define MIPS_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
+#define MIPS_CONFIG_CACHE_SIZE(config, mask, base, shift) \
((base) << (((config) & (mask)) >> (shift)))
/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
-#define MIPS3_CONFIG_SE 0x00001000
+#define MIPS_CONFIG_SE 0x00001000
/* Block ordering: 0: sequential, 1: sub-block */
-#define MIPS3_CONFIG_EB 0x00002000
+#define MIPS_CONFIG_EB 0x00002000
/* ECC mode - 0: ECC mode, 1: parity mode */
-#define MIPS3_CONFIG_EM 0x00004000
+#define MIPS_CONFIG_EM 0x00004000
/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
-#define MIPS3_CONFIG_BE 0x00008000
+#define MIPS_CONFIG_BE 0x00008000
/* Dirty Shared coherency state - 0: enabled, 1: disabled */
-#define MIPS3_CONFIG_SM 0x00010000
+#define MIPS_CONFIG_SM 0x00010000
/* Secondary Cache - 0: present, 1: not present */
-#define MIPS3_CONFIG_SC 0x00020000
+#define MIPS_CONFIG_SC 0x00020000
/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
-#define MIPS3_CONFIG_EW_MASK 0x000c0000
-#define MIPS3_CONFIG_EW_SHIFT 18
+#define MIPS_CONFIG_EW_MASK 0x000c0000
+#define MIPS_CONFIG_EW_SHIFT 18
/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
-#define MIPS3_CONFIG_SW 0x00100000
+#define MIPS_CONFIG_SW 0x00100000
/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
-#define MIPS3_CONFIG_SS 0x00200000
+#define MIPS_CONFIG_SS 0x00200000
/* Secondary Cache line size */
-#define MIPS3_CONFIG_SB_MASK 0x00c00000
-#define MIPS3_CONFIG_SB_SHIFT 22
-#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
- (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
+#define MIPS_CONFIG_SB_MASK 0x00c00000
+#define MIPS_CONFIG_SB_SHIFT 22
+#define MIPS_CONFIG_CACHE_L2_LSIZE(config) \
+ (0x10 << (((config) & MIPS_CONFIG_SB_MASK) >> MIPS_CONFIG_SB_SHIFT))
/* Write back data rate */
-#define MIPS3_CONFIG_EP_MASK 0x0f000000
-#define MIPS3_CONFIG_EP_SHIFT 24
+#define MIPS_CONFIG_EP_MASK 0x0f000000
+#define MIPS_CONFIG_EP_SHIFT 24
/* System clock ratio - this value is CPU dependent */
-#define MIPS3_CONFIG_EC_MASK 0x70000000
-#define MIPS3_CONFIG_EC_SHIFT 28
+#define MIPS_CONFIG_EC_MASK 0x70000000
+#define MIPS_CONFIG_EC_SHIFT 28
/* Master-Checker Mode - 1: enabled */
-#define MIPS3_CONFIG_CM 0x80000000
+#define MIPS_CONFIG_CM 0x80000000
/*
* Location of exception vectors.
@@ -341,14 +321,14 @@
/*
* MIPS-III exception vectors
*/
-#define MIPS3_XTLB_MISS_EXC_VEC 0xFFFFFFFF80000080
-#define MIPS3_CACHE_ERR_EXC_VEC 0xFFFFFFFF80000100
-#define MIPS3_GEN_EXC_VEC 0xFFFFFFFF80000180
+#define MIPS_XTLB_MISS_EXC_VEC 0xFFFFFFFF80000080
+#define MIPS_CACHE_ERR_EXC_VEC 0xFFFFFFFF80000100
+#define MIPS_GEN_EXC_VEC 0xFFFFFFFF80000180
/*
* MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
*/
-#define MIPS3_INTR_EXC_VEC 0xFFFFFFFF80000200
+#define MIPS_INTR_EXC_VEC 0xFFFFFFFF80000200
/*
* Coprocessor 0 registers:
@@ -472,7 +452,7 @@
*/
#define MIPS_MIN_CACHE_SIZE (16 * 1024)
#define MIPS_MAX_CACHE_SIZE (256 * 1024)
-#define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
+#define MIPS_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
/*
* The floating point version and status registers.
@@ -509,7 +489,7 @@
#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
#define MIPS_FPU_COND_BIT 0x00800000
#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
-#define MIPS3_FPC_MBZ_BITS 0xfe7c0000
+#define MIPS_FPC_MBZ_BITS 0xfe7c0000
/*
@@ -521,12 +501,8 @@
/*
* The number of process id entries.
*/
-#define MIPS3_TLB_NUM_ASIDS 256
-
-/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
-
+#define MIPS_TLB_NUM_ASIDS 256
#define MIPS_TLB_PID_SHIFT 0
-#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
/*
* CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
==== //depot/projects/mips/sys/mips/mips/cache.c#6 (text+ko) ====
@@ -224,7 +224,7 @@
void
mips_config_cache_prehistoric(void)
{
- int csizebase = MIPS3_CONFIG_C_DEFBASE;
+ int csizebase = MIPS_CONFIG_C_DEFBASE;
KASSERT(PAGE_SIZE != 0, ("sane page size"));
@@ -448,8 +448,8 @@
* is ignored wrt VCED/VCEI.
*/
mips_cache_alias_mask =
- (MIPS3_MAX_PCACHE_SIZE - 1) & ~(PAGE_SIZE - 1);
- mips_cache_prefer_mask = MIPS3_MAX_PCACHE_SIZE - 1;
+ (MIPS_MAX_PCACHE_SIZE - 1) & ~(PAGE_SIZE - 1);
+ mips_cache_prefer_mask = MIPS_MAX_PCACHE_SIZE - 1;
/* FALLTHROUGH */
case MIPS_R4100:
case MIPS_R4300:
@@ -565,15 +565,15 @@
config = mips_rd_config();
- mips_picache_size = MIPS3_CONFIG_CACHE_SIZE(config,
- MIPS3_CONFIG_IC_MASK, csizebase, MIPS3_CONFIG_IC_SHIFT);
- mips_picache_line_size = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
- MIPS3_CONFIG_IB);
+ mips_picache_size = MIPS_CONFIG_CACHE_SIZE(config,
+ MIPS_CONFIG_IC_MASK, csizebase, MIPS_CONFIG_IC_SHIFT);
+ mips_picache_line_size = MIPS_CONFIG_CACHE_L1_LSIZE(config,
+ MIPS_CONFIG_IB);
- mips_pdcache_size = MIPS3_CONFIG_CACHE_SIZE(config,
- MIPS3_CONFIG_DC_MASK, csizebase, MIPS3_CONFIG_DC_SHIFT);
- mips_pdcache_line_size = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
- MIPS3_CONFIG_DB);
+ mips_pdcache_size = MIPS_CONFIG_CACHE_SIZE(config,
+ MIPS_CONFIG_DC_MASK, csizebase, MIPS_CONFIG_DC_SHIFT);
+ mips_pdcache_line_size = MIPS_CONFIG_CACHE_L1_LSIZE(config,
+ MIPS_CONFIG_DB);
mips_cache_alias_mask =
((mips_pdcache_size / mips_pdcache_ways) - 1) & ~(PAGE_SIZE - 1);
@@ -595,12 +595,12 @@
* L2 is usable. If the L2 is disabled, we treat it the same
* as if there were no L2 cache.
*/
- if ((config & MIPS3_CONFIG_SC) == 0) {
+ if ((config & MIPS_CONFIG_SC) == 0) {
if (has_sdcache_enable == 0 ||
- (has_sdcache_enable && (config & MIPS3_CONFIG_SE))) {
+ (has_sdcache_enable && (config & MIPS_CONFIG_SE))) {
mips_sdcache_line_size =
- MIPS3_CONFIG_CACHE_L2_LSIZE(config);
- if ((config & MIPS3_CONFIG_SS) == 0)
+ MIPS_CONFIG_CACHE_L2_LSIZE(config);
+ if ((config & MIPS_CONFIG_SS) == 0)
mips_scache_unified = 1;
} else {
#ifdef CACHE_DEBUG
==== //depot/projects/mips/sys/mips/mips/cache_mipsNN.c#2 (text+ko) ====
==== //depot/projects/mips/sys/mips/mips/cache_r5k_subr.S#3 (text+ko) ====
@@ -56,7 +56,7 @@
1:
mfc0 v0, MIPS_COP_0_CONFIG
- or v1, v0, MIPS3_CONFIG_SE
+ or v1, v0, MIPS_CONFIG_SE
mtc0 v1, MIPS_COP_0_CONFIG # enable the secondary cache
nop
nop
==== //depot/projects/mips/sys/mips/mips/locore.S#9 (text+ko) ====
@@ -58,13 +58,13 @@
* Soft reset
* Boot exception vectors (firmware-provided)
*/
- li t0, MIPS_SR_BEV | MIPS3_SR_SR
+ li t0, MIPS_SR_BEV | MIPS_SR_SR
/*
* t1: Bits to set explicitly:
* Kernel mode is 64-bit
* Enable FPU
*/
- li t1, MIPS3_SR_KX | MIPS_SR_COP_1_BIT
+ li t1, MIPS_SR_KX | MIPS_SR_COP_1_BIT
/*
* Read coprocessor 0 status register, clear bits not
==== //depot/projects/mips/sys/mips/mips/machdep.c#39 (text+ko) ====
@@ -359,8 +359,6 @@
* XXX begin NetBSD stuff, I want to rewrite or move out most.
*/
-static void mips64_vector_init(void);
-
struct pridtab {
int cpu_cid;
int cpu_pid;
@@ -376,10 +374,10 @@
* Assumptions:
* - All MIPS3+ have an r4k-style MMU. _Many_ assumptions throughout
* much of the mips code about this. Includes overloaded usage of
- * MIPS3_PLUS.
+ * MIPS_PLUS.
* - All MIPS3+ use the same exception model (cp0 status, cause bits,
* etc). _Many_ assumptions throughout much of the mips code about
- * this. Includes overloaded usage of MIPS3_PLUS.
+ * this. Includes overloaded usage of MIPS_PLUS.
* - All MIPS3+ have a count register. MIPS_HAS_CLOCK in <mips/cpu.h>
* will need to be revised if this is false.
*/
@@ -573,7 +571,7 @@
#define ncidnames (sizeof(cidnames) / sizeof(cidnames[0]))
static void
-mips64_vector_install(vm_offset_t addr, char *begin, char *end)
+mips_vector_install(vm_offset_t addr, char *begin, char *end)
{
size_t len, max;
@@ -598,32 +596,6 @@
/* Cache error handler */
extern char CacheVector[], CacheVectorEnd[];
-static void
-mips64_vector_init(void)
-{
- /*
- * Copy down exception vector code.
- */
-
- mips64_vector_install(MIPS_UTLB_MISS_EXC_VEC,
- TLBMissVector, TLBMissVectorEnd);
- mips64_vector_install(MIPS3_XTLB_MISS_EXC_VEC,
- XTLBMissVector, XTLBMissVectorEnd);
- mips64_vector_install(MIPS3_CACHE_ERR_EXC_VEC,
- CacheVector, CacheVectorEnd);
- mips64_vector_install(MIPS3_GEN_EXC_VEC,
- ExceptionVector, ExceptionVectorEnd);
- /* XXX do a real interrupt vector for the mips32/64? */
- mips64_vector_install(MIPS3_INTR_EXC_VEC,
- ExceptionVector, ExceptionVectorEnd);
-
- mips_icache_sync_all();
- mips_dcache_wbinv_all();
-
- /* Clear BEV in SR so we start handling our own exceptions */
- mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
-}
-
/*
* Do all the stuff that locore normally does before calling main(),
* that is common to all mips-CPU NetBSD ports.
@@ -736,14 +708,35 @@
switch (cpu_arch) {
case CPU_ARCH_MIPS3:
case CPU_ARCH_MIPS64:
- mips_wr_wired(0);
- tlb_invalidate_all();
- mips64_vector_init();
break;
default:
printf("cpu_arch 0x%x: not supported\n", cpu_arch);
cpu_halt();
}
+
+ tlb_invalidate_all();
+
+ /*
+ * Copy down exception vector code.
+ */
+
+ mips_vector_install(MIPS_UTLB_MISS_EXC_VEC,
+ TLBMissVector, TLBMissVectorEnd);
+ mips_vector_install(MIPS_XTLB_MISS_EXC_VEC,
+ XTLBMissVector, XTLBMissVectorEnd);
+ mips_vector_install(MIPS_CACHE_ERR_EXC_VEC,
+ CacheVector, CacheVectorEnd);
+ mips_vector_install(MIPS_GEN_EXC_VEC,
+ ExceptionVector, ExceptionVectorEnd);
+ /* XXX do a real interrupt vector for the mips32/64? */
+ mips_vector_install(MIPS_INTR_EXC_VEC,
+ ExceptionVector, ExceptionVectorEnd);
+
+ mips_icache_sync_all();
+ mips_dcache_wbinv_all();
+
+ /* Clear BEV in SR so we start handling our own exceptions */
+ mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
}
/*
==== //depot/projects/mips/sys/mips/mips/tlb.c#16 (text+ko) ====
@@ -63,7 +63,7 @@
/*
* XXX Move the ASID code here.
*/
-static int tlb_maxasid = MIPS3_TLB_NUM_ASIDS;
+static int tlb_maxasid = MIPS_TLB_NUM_ASIDS;
#endif
void
==== //depot/projects/mips/sys/mips/mips/trap.c#14 (text+ko) ====
@@ -96,7 +96,7 @@
platform_trap_enter();
- code = (cause & MIPS3_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT;
+ code = (cause & MIPS_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT;
kernelmode = (tf->tf_regs[TF_SR] & MIPS_SR_KSU_USER) == 0;
/*
@@ -132,6 +132,13 @@
printf("cause = %#x\n", cause);
printf("status = %#lx\n", tf->tf_regs[TF_SR]);
printf("current thread = %p\n", curthread);
+ printf("current process = ");
+ if (curproc != NULL) {
+ printf("%d", curproc->p_pid);
+ printf(" (%s)", curproc->p_comm);
+ } else
+ printf("%p", curproc);
+ printf("\n");
switch (code) {
case T_BREAK:
==== //depot/projects/mips/sys/mips/sgimips/ip22_cache.S#2 (text+ko) ====
@@ -53,7 +53,7 @@
nop ; \
li v0, ~MIPS_SR_INT_IE /* ints off */ ; \
and t1, v0, t0 ; \
- or t1, MIPS3_SR_KX /* enable 64-bit */ ; \
+ or t1, MIPS_SR_KX /* enable 64-bit */ ; \
mtc0 t1, MIPS_COP_0_STATUS ; \
nop ; \
nop ; \
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