PERFORCE change 30405 for review
Marcel Moolenaar
marcel at FreeBSD.org
Fri May 2 11:27:28 PDT 2003
http://perforce.freebsd.org/chv.cgi?CH=30405
Change 30405 by marcel at marcel_nfs on 2003/05/02 11:27:14
Replace the barrier comments with real barriers. Abstract the
bus space interface by using a slightly more convenient
sio_barrier() macro.
Affected files ...
.. //depot/projects/sio/sys/dev/sio/sio.c#3 edit
.. //depot/projects/sio/sys/dev/sio/sio_cons.c#2 edit
.. //depot/projects/sio/sys/dev/sio/siovar.h#3 edit
Differences ...
==== //depot/projects/sio/sys/dev/sio/sio.c#3 (text+ko) ====
@@ -316,7 +316,7 @@
limit=32768;
while ((sio_getreg(com, com_lsr) & LSR_RXRDY) && --limit) {
(void)sio_getreg(com, com_data);
- /* XXX barrier */
+ sio_barrier(com);
DELAY(5*delay);
}
if (limit == 0) {
@@ -370,7 +370,7 @@
* any data from being sent.
*/
sio_setreg(com, com_mcr, com->reg_mcr | MCR_LOOPBACK|MCR_DTR|MCR_RTS);
- /* XXX barrier */
+ sio_barrier(com);
/*
* Enable FIFOs. Set DMA mode with the highest trigger level so
@@ -379,13 +379,13 @@
*/
com->reg_fcr = FCR_ENABLE | FCR_DMA_MODE | FCR_RX_HIGH;
sio_setreg(com, com_fcr, com->reg_fcr | FCR_XMT_RST | FCR_RCV_RST);
- /* XXX barrier */
+ sio_barrier(com);
/* Check if the UART has FIFOs. If not, we're done. */
com->hasfifo = (sio_getreg(com, com_iir) & IIR_FIFO_MASK) ? 1 : 0;
if (!com->hasfifo) {
sio_setreg(com, com_mcr, com->reg_mcr);
- /* XXX barrier */
+ sio_barrier(com);
siodebug(NULL, "no FIFOs... ");
return (0);
}
@@ -393,12 +393,12 @@
/* We have FIFOs. Flush the transmitter and receiver. */
if (sioflush(com)) {
sio_setreg(com, com_mcr, com->reg_mcr);
- /* XXX barrier */
+ sio_barrier(com);
goto fallback;
}
sio_setreg(com, com_ier, IER_ERXRDY);
- /* XXX barrier */
+ sio_barrier(com);
/*
* We should have a sufficiently clean "pipe" to determine the
@@ -410,7 +410,7 @@
count = 0;
while ((sio_getreg(com, com_iir) & IIR_RXRDY) == 0 && count < 1030) {
sio_setreg(com, com_data, 0);
- /* XXX barrier */
+ sio_barrier(com);
count++;
limit = 30;
@@ -420,24 +420,24 @@
}
if (limit == 0) {
sio_setreg(com, com_ier, 0);
- /* XXX barrier */
+ sio_barrier(com);
sio_setreg(com, com_mcr, com->reg_mcr);
- /* XXX barrier */
+ sio_barrier(com);
siodebug(NULL, "can't determine FIFO size... ");
goto fallback;
}
}
sio_setreg(com, com_ier, 0);
- /* XXX barrier */
+ sio_barrier(com);
/* Reset FIFOs. */
com->reg_fcr = FCR_ENABLE;
sio_setreg(com, com_fcr, com->reg_fcr | FCR_XMT_RST | FCR_RCV_RST);
- /* XXX barrier */
+ sio_barrier(com);
sio_setreg(com, com_mcr, com->reg_mcr);
- /* XXX barrier */
+ sio_barrier(com);
if (count >= 14 && count < 16)
com->fifosize = 16; /* 16550 */
@@ -504,11 +504,11 @@
*/
spr = sio_getreg(com, com_scr);
sio_setreg(com, com_scr, ~spr);
- /* XXX barrier */
+ sio_barrier(com);
has_spr = (sio_getreg(com, com_scr) == ~spr) ? 1 : 0;
- /* XXX barrier */
+ sio_barrier(com);
sio_setreg(com, com_scr, spr);
- /* XXX barrier */
+ sio_barrier(com);
if (!has_spr)
device_set_desc(com->dev, "8250 or compatible");
else
@@ -571,14 +571,14 @@
/* XXX we can do more. */
sio_setreg(com, com_ier, 0);
- /* XXX barrier */
+ sio_barrier(com);
sio_setreg(com, com_lcr, lcr);
- /* XXX barrier */
+ sio_barrier(com);
return (0);
fail:
sio_setreg(com, com_lcr, lcr);
- /* XXX barrier */
+ sio_barrier(com);
return (ENXIO);
}
@@ -678,17 +678,17 @@
com->rclk = DEFAULT_RCLK;
sio_setreg(com, com_fcr, 0);
- /* XXX barrier */
+ sio_barrier(com);
sio_setreg(com, com_lcr, LCR_8BITS | LCR_DLAB);
- /* XXX barrier */
+ sio_barrier(com);
com->reg_dl = siodivisor(com->rclk, comdefaultrate);
sio_setdreg(com, com_dl, com->reg_dl);
- /* XXX barrier */
+ sio_barrier(com);
sio_setreg(com, com_lcr, LCR_8BITS);
- /* XXX barrier */
+ sio_barrier(com);
com->reg_mcr = MCR_IENABLE;
sio_setreg(com, com_mcr, com->reg_mcr);
- /* XXX barrier */
+ sio_barrier(com);
}
/* Initialize the FIFOs. */
==== //depot/projects/sio/sys/dev/sio/sio_cons.c#2 (text+ko) ====
@@ -139,15 +139,15 @@
/* Set DL and LCR. */
lcr = siocnlcr(&cd);
sio_setreg(&sio_console, com_lcr, lcr | LCR_DLAB);
- /* XXX barrier */
+ sio_barrier(&sio_console);
if (cd.baud != 0) {
divisor = siodivisor(sio_console.rclk, cd.baud);
sio_setdreg(&sio_console, com_dl, divisor);
} else
divisor = sio_getdreg(&sio_console, com_dl);
- /* XXX barrier */
+ sio_barrier(&sio_console);
sio_setreg(&sio_console, com_lcr, lcr);
- /* XXX barrier */
+ sio_barrier(&sio_console);
sio_console.reg_dl = divisor;
@@ -161,17 +161,17 @@
/* Disable all interrupt sources. */
sio_setreg(&sio_console, com_ier, 0);
- /* XXX barrier */
+ sio_barrier(&sio_console);
/* Disable the FIFO (if present). */
sio_console.reg_fcr = 0;
sio_setreg(&sio_console, com_fcr, sio_console.reg_fcr);
- /* XXX barrier */
+ sio_barrier(&sio_console);
/* Set MCR. */
sio_console.reg_mcr = MCR_IENABLE | MCR_RTS | MCR_DTR;
sio_setreg(&sio_console, com_mcr, sio_console.reg_mcr);
- /* XXX barrier */
+ sio_barrier(&sio_console);
/*
* Clear pending interrupts. THRE is cleared by reading IIR. Data
@@ -186,10 +186,10 @@
sio_getreg(&sio_console, com_rbr);
else if (iir == IIR_MLSC)
sio_getreg(&sio_console, com_msr);
- /* XXX barrier */
+ sio_barrier(&sio_console);
iir = sio_getreg(&sio_console, com_iir);
}
- /* XXX barrier */
+ sio_barrier(&sio_console);
/* It's official... */
sio_console.consdev = cp;
==== //depot/projects/sio/sys/dev/sio/siovar.h#3 (text+ko) ====
@@ -176,6 +176,10 @@
#define sio_setdreg(com, reg, value) \
bus_space_write_2((com)->bst, (com)->bsh, sio_offset(com, reg), value)
+#define sio_barrier(com) \
+ bus_space_barrier((com)->bst, (com)->bsh, 0, sio_offset(com, 8), \
+ BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
+
#define SET_FLAG(dev, bit) \
device_set_flags(dev, device_get_flags(dev) | (bit))
#define CLR_FLAG(dev, bit) \
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