PERFORCE change 30000 for review
Juli Mallett
jmallett at FreeBSD.org
Mon Apr 28 16:13:13 PDT 2003
http://perforce.freebsd.org/chv.cgi?CH=30000
Change 30000 by jmallett at jmallett_dalek on 2003/04/28 16:12:08
Add mips_subr and requirements to link.
Affected files ...
.. //depot/projects/mips/sys/conf/files.mips#15 edit
.. //depot/projects/mips/sys/mips/include/pcpu.h#3 edit
.. //depot/projects/mips/sys/mips/mips/machdep.c#16 edit
.. //depot/projects/mips/sys/mips/mips/mips_subr.S#2 edit
.. //depot/projects/mips/sys/mips/mips/pmap.c#8 edit
Differences ...
==== //depot/projects/mips/sys/conf/files.mips#15 (text+ko) ====
@@ -15,10 +15,13 @@
mips/mips/locore.S standard no-obj
mips/mips/locore_mips3.S standard
mips/mips/machdep.c standard
+mips/mips/mips_subr.S standard
mips/mips/pmap.c standard
mips/mips/sig_machdep.c standard
mips/mips/support.S standard
mips/mips/sys_machdep.c standard
+mips/mips/syscall.c standard
+mips/mips/trap.c standard
mips/mips/vm_machdep.c standard
# XXX cache code needs to be split up per CPU type, but yuck.
mips/mips/cache.c standard
==== //depot/projects/mips/sys/mips/include/pcpu.h#3 (text+ko) ====
@@ -37,13 +37,13 @@
#define PCPU_MD_FIELDS \
/* XXX Nothing to see here. */
-#define PCPUP ((struct pcpu *) &pcpu0)
+#define PCPUP (pcpup)
#define PCPU_GET(member) (PCPUP->pc_ ## member)
#define PCPU_PTR(member) (&PCPUP->pc_ ## member)
#define PCPU_SET(member,value) (PCPUP->pc_ ## member = (value))
-extern struct pcpu pcpu0;
+extern struct pcpu *pcpup;
#endif /* _KERNEL */
==== //depot/projects/mips/sys/mips/mips/machdep.c#16 (text+ko) ====
@@ -150,6 +150,7 @@
#include <sys/ucontext.h>
#include <sys/proc.h>
#include <sys/ptrace.h>
+#include <sys/reboot.h>
#include <sys/user.h>
#include <machine/cache.h>
@@ -173,7 +174,8 @@
int cold = 1;
int cpu_id, fpu_id;
-struct pcpu pcpu0;
+static struct pcpu pcpu0;
+struct pcpu *pcpup = &pcpu0;
vm_offset_t kstack0;
vm_paddr_t kstack0_phys;
@@ -181,14 +183,11 @@
void
mips_init(void)
{
- struct pcpu *pc;
-
mips_vector_init();
cpu_identify();
proc_linkup(&proc0, &ksegrp0, &kse0, &thread0);
thread0.td_kstack = kstack0;
- pc = &pcpu0;
- pc->pc_curthread = &thread0;
+ pcpup->pc_curthread = &thread0;
}
void
@@ -297,11 +296,12 @@
return (-1);
}
-#if 0
+static void mips64_vector_init(void);
+extern long *mips64_locoresw[];
+
mips_locore_jumpvec_t mips_locore_jumpvec;
long *mips_locoresw[3];
-#endif
struct pridtab {
int cpu_cid;
@@ -520,7 +520,6 @@
};
#define ncidnames (sizeof(cidnames) / sizeof(cidnames[0]))
-#ifdef notyet
/*
* MIPS64 locore function vector
*/
@@ -595,7 +594,6 @@
/* Clear BEV in SR so we start handling our own exceptions */
mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV);
}
-#endif /* notyet */
/*
* Do all the stuff that locore normally does before calling main(),
@@ -712,7 +710,6 @@
*/
mips_config_cache();
-#if notyet
/*
* Now initialize our ISA-dependent function vector.
*/
@@ -726,7 +723,7 @@
break;
default:
printf("cpu_arch 0x%x: not supported\n", cpu_arch);
- cpu_reboot(RB_HALT, NULL);
+ cpu_halt();
}
/* XXX simonb: ugg, another ugly #ifdef check... */
@@ -736,10 +733,8 @@
if ((mips_cpu_flags & CPU_MIPS_USE_WAIT) &&
!(mips_cpu_flags & CPU_MIPS_NO_WAIT))
CPU_IDLE = (long *)mips_wait_idle;
-#endif /* notyet */
}
-#if notyet
void
mips_set_wbflush(flush_fn)
void (*flush_fn)(void);
@@ -748,7 +743,6 @@
mips_locore_jumpvec.wbflush = flush_fn;
(*flush_fn)();
}
-#endif
/*
* Identify product revision IDs of cpu and fpu.
==== //depot/projects/mips/sys/mips/mips/mips_subr.S#2 (text+ko) ====
@@ -586,7 +586,8 @@
/*
* Save all of the registers except for the kernel temporaries in u_pcb.
*/
- lw k1, curpcb
+ la k1, pcpup
+ ld k1, PC_CURPCB(k1)
#nop # -slip-
addu k1, k1, USPACE - FRAME_SIZ
REG_S AT, FRAME_AST(k1)
@@ -654,11 +655,10 @@
/*
* Check pending asynchronous traps.
*/
- lw t0, curlwp # t0 = curlwp
- nop
- lw t0, L_PROC(t0) # t0 = curlwp->l_proc
- nop
- lw t0, P_MD_ASTPENDING(t0)
+ la t0, pcpup
+ ld t0, PC_CURTHREAD(t0)
+ lw t0, TD_FLAGS(t0)
+ and t0, TDF_ASTPENDING
beq t0, zero, 1f
nop
/*
@@ -750,7 +750,8 @@
NESTED_NOPROFILE(MIPSX(SystemCall), CALLFRAME_SIZ, ra)
.set noat
.mask 0x80000000, -4
- lw k1, curpcb
+ la k1, pcpup
+ ld k1, PC_CURPCB(k1)
#nop # -slip-
addu k1, k1, USPACE - FRAME_SIZ
#REG_S AT, FRAME_AST(k1)
@@ -761,7 +762,8 @@
REG_S a1, FRAME_A1(k1)
REG_S a2, FRAME_A2(k1)
REG_S a3, FRAME_A3(k1)
- lw a0, curlwp # 1st arg is curlwp
+ la a0, pcpup
+ ld a0, PC_CURTHREAD(a0)
mfhi v1
#REG_S t0, FRAME_T0(k1) # no need to save temp regs
#REG_S t1, FRAME_T1(k1)
@@ -798,7 +800,7 @@
sw t0, FRAME_PPL(k1)
.set noat
#endif
- lw t0, L_PROC(a0) # curlwp->l_proc (used below)
+ ld t0, TD_PROC(a0)
addu sp, k1, -CALLFRAME_SIZ
#ifdef __GP_SUPPORT__
la gp, _gp # switch to kernel GP
@@ -807,7 +809,6 @@
* Turn off fpu and enter kernel mode
*/
.set at
- lw t1, P_MD_SYSCALL(t0) # t1 = syscall
and t0, a1, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS_SR_KSU_MASK)
.set noat
#if defined(DDB) || defined(DEBUG) || defined(KGDB)
@@ -819,14 +820,15 @@
*/
mtc0 t0, MIPS_COP_0_STATUS # re-enable interrupts
COP0_SYNC
- jal t1
+ jal syscall_enter
nop
/*
* Check pending asynchronous traps.
*/
- lw t0, curlwp
- lw t0, L_PROC(t0)
- lw t0, P_MD_ASTPENDING(t0) # curlwp->l_proc->p_md.md_astpending
+ la t0, pcpup
+ ld t0, PC_CURTHREAD(t0)
+ lw t0, TD_FLAGS(t0)
+ and t0, TDF_ASTPENDING
beq t0, zero, 1f
nop
/*
@@ -1088,7 +1090,8 @@
* Save the relevant user registers into the u_pcb.
* We don't need to save s0 - s8 because the compiler does it for us.
*/
- lw k1, curpcb
+ la k1, pcpup
+ ld k1, PC_CURPCB(k1)
#nop # -slip-
addu k1, k1, USPACE - FRAME_SIZ
REG_S AT, FRAME_AST(k1)
@@ -1162,11 +1165,12 @@
nop # 3 nop hazard
nop
nop
- lw v0, curlwp
+ la v0, pcpup
+ ld v0, PC_CURTHREAD(v0)
addu a1, sp, CALLFRAME_SIZ
- lw v0, L_PROC(v0)
+ lw v0, TD_FLAGS
# REG_L a0, FRAME_SR(a1)
- lw v0, P_MD_ASTPENDING(v0) # any pending ast?
+ and v0, TDF_ASTPENDING # any pending ast?
# mtc0 a0, MIPS_COP_0_STATUS # restore the SR, disable intrs
/*
* Check pending asynchronous traps.
@@ -1314,11 +1318,11 @@
li k1, VM_MIN_KERNEL_ADDRESS # compute index
bgez k0, MIPSX(KernGenException) # full trap processing
subu k0, k0, k1
- lw k1, Sysmapsize # index within range?
+ lw k1, kptemapsize # index within range?
srl k0, k0, PGSHIFT
sltu k1, k0, k1
beq k1, zero, outofworld # No. Failing beyond. . .
- lw k1, Sysmap
+ ld k1, kptemap
sll k0, k0, 2 # compute offset from index
addu k1, k1, k0
@@ -1414,7 +1418,7 @@
_MFC0 k0, MIPS_COP_0_BAD_VADDR # get the fault address
li k1, VM_MIN_KERNEL_ADDRESS # compute index
subu k0, k0, k1
- lw k1, Sysmapsize # index within range?
+ lw k1, kptemapsize # index within range?
srl k0, k0, PGSHIFT
sltu k1, k0, k1
#ifdef newsmips
@@ -1426,7 +1430,7 @@
#else
beq k1, zero, outofworld # No. Failing beyond. . .
#endif
- lw k1, Sysmap
+ ld k1, kptemap
srl k0, k0, 1
sll k0, k0, 3 # compute offset from index
addu k1, k1, k0
@@ -1781,9 +1785,10 @@
* sure TBIS(it) in the case.
*/
LEAF_NOPROFILE(MIPSX(cpu_switch_resume))
- lw a1, L_MD_UPTE_0(a0) # a1 = upte[0]
- lw a2, L_MD_UPTE_1(a0) # a2 = upte[1]
- lw v0, L_ADDR(a0) # va = l->l_addr
+ lw a1, TD_MD_UPTE_0(a0) # a1 = upte[0]
+ lw a2, TD_MD_UPTE_1(a0) # a2 = upte[1]
+ ld v0, TD_PROC(a0) # v0 = td->proc
+ ld v0, P_UAREA(v0) # va = v0->p_uarea
li s0, MIPS_KSEG2_START
blt v0, s0, resume
nop
==== //depot/projects/mips/sys/mips/mips/pmap.c#8 (text+ko) ====
@@ -61,6 +61,8 @@
pt_entry_t *kptemap;
vm_size_t kptemapsize;
+struct segtab *segbase;
+
struct msgbuf *msgbufp;
int pmap_pagedaemon_waken;
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