PERFORCE change 29955 for review

[Juli Mallett]

http://perforce.freebsd.org/chv.cgi?CH=29955

Change 29955 by jmallett at jmallett_dalek on 2003/04/28 11:12:43

	Useful macros from NetBSD.

Affected files ...

.. //depot/projects/mips/sys/mips/include/asm.h#5 edit

Differences ...

==== //depot/projects/mips/sys/mips/include/asm.h#5 (text+ko) ====

@@ -105,4 +105,52 @@
 	.section .gnu.warning./**/_sym ; .ascii _msg ; .text
 #endif /* __STDC__ */
 
+/*
+ *  standard callframe {
+ *  	register_t cf_args[4];		arg0 - arg3
+ *  	register_t cf_sp;		frame pointer
+ *  	register_t cf_ra;		return address
+ *  };
+ */
+#define	CALLFRAME_SIZ	(4 * (4 + 2))
+#define	CALLFRAME_SP	(4 * 4)
+#define	CALLFRAME_RA	(4 * 5)
+
+/*
+ * While it would be nice to be compatible with the SGI
+ * REG_L and REG_S macros, because they do not take parameters, it
+ * is impossible to use them with the _MIPS_SIM_ABIX32 model.
+ *
+ * These macros hide the use of mips3 instructions from the
+ * assembler to prevent the assembler from generating 64-bit style
+ * ABI calls.
+ */
+#define	REG_L	ld
+#define REG_S	sd
+#define	REG_LI	dli
+#define SZREG	8
+
+/*
+ * The DYNAMIC_STATUS_MASK option adds an additional masking operation
+ * when updating the hardware interrupt mask in the status register.
+ *
+ * This is useful for platforms that need to at run-time mask
+ * interrupts based on motherboard configuration or to handle
+ * slowly clearing interrupts.
+ *
+ * XXX this is only currently implemented for mips3.
+ */
+#ifdef MIPS_DYNAMIC_STATUS_MASK
+#define DYNAMIC_STATUS_MASK(sr,scratch)	\
+	lw	scratch, mips_dynamic_status_mask; \
+	and	sr, sr, scratch
+
+#define DYNAMIC_STATUS_MASK_TOUSER(sr,scratch1)		\
+	ori	sr, (MIPS_INT_MASK | MIPS_SR_INT_IE);	\
+	DYNAMIC_STATUS_MASK(sr,scratch1)
+#else
+#define DYNAMIC_STATUS_MASK(sr,scratch)
+#define DYNAMIC_STATUS_MASK_TOUSER(sr,scratch1)
+#endif
+
 #endif /* !_MACHINE_ASM_H_ */