PERFORCE change 29922 for review
Juli Mallett
jmallett at FreeBSD.org
Sun Apr 27 20:32:32 PDT 2003
http://perforce.freebsd.org/chv.cgi?CH=29922
Change 29922 by jmallett at jmallett_dalek on 2003/04/27 20:31:36
Oops; compile.
Affected files ...
.. //depot/projects/mips/sys/mips/include/cache_r4k.h#2 edit
.. //depot/projects/mips/sys/mips/include/cache_r5k.h#2 edit
.. //depot/projects/mips/sys/mips/mips/cache.c#2 edit
.. //depot/projects/mips/sys/mips/mips/cache_r5k.c#2 edit
.. //depot/projects/mips/sys/mips/mips/cache_r5k_subr.S#2 edit
Differences ...
==== //depot/projects/mips/sys/mips/include/cache_r4k.h#2 (text+ko) ====
@@ -55,7 +55,7 @@
#define CACHEOP_R4K_HIT_WB (6 << 2) /* I, D, SD */
#define CACHEOP_R4K_HIT_SET_VIRTUAL (7 << 2) /* SI, SD */
-#if !defined(_LOCORE)
+#if !defined(LOCORE)
/*
* cache_r4k_op_line:
@@ -378,4 +378,4 @@
void r4k_sdcache_inv_range_generic(vm_paddr_t, vm_size_t);
void r4k_sdcache_wb_range_generic(vm_paddr_t, vm_size_t);
-#endif /* !_LOCORE */
+#endif /* !LOCORE */
==== //depot/projects/mips/sys/mips/include/cache_r5k.h#2 (text+ko) ====
@@ -35,7 +35,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#if defined(_KERNEL) && !defined(_LOCORE)
+#if defined(_KERNEL) && !defined(LOCORE)
void r5k_icache_sync_all_32(void);
void r5k_icache_sync_range_32(vm_paddr_t, vm_size_t);
@@ -68,4 +68,4 @@
void r5k_sdcache_inv_range(vm_paddr_t, vm_size_t);
void r5k_sdcache_wb_range(vm_paddr_t, vm_size_t);
-#endif /* _KERNEL && !_LOCORE */
+#endif /* _KERNEL && !LOCORE */
==== //depot/projects/mips/sys/mips/mips/cache.c#2 (text+ko) ====
==== //depot/projects/mips/sys/mips/mips/cache_r5k.c#2 (text+ko) ====
@@ -37,10 +37,12 @@
#include <sys/param.h>
-#include <mips/cache.h>
-#include <mips/cache_r4k.h>
-#include <mips/cache_r5k.h>
-#include <mips/locore.h>
+#include <machine/cache.h>
+#include <machine/cache_r4k.h>
+#include <machine/cache_r5k.h>
+#include <machine/cpu.h>
+#include <machine/cpuregs.h>
+#include <machine/locore.h>
/*
* Cache operations for R5000-style caches:
@@ -85,8 +87,8 @@
void
r5k_icache_sync_all_32(void)
{
- vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
- vaddr_t eva = va + mips_picache_size;
+ vm_paddr_t va = MIPS_PHYS_TO_KSEG0(0);
+ vm_paddr_t eva = va + mips_picache_size;
/*
* Since we're hitting the whole thing, we don't have to
@@ -104,9 +106,9 @@
}
void
-r5k_icache_sync_range_32(vaddr_t va, vsize_t size)
+r5k_icache_sync_range_32(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line(va + size);
+ vm_paddr_t eva = round_line(va + size);
va = trunc_line(va);
@@ -126,9 +128,9 @@
}
void
-r5k_icache_sync_range_index_32(vaddr_t va, vsize_t size)
+r5k_icache_sync_range_index_32(vm_paddr_t va, vm_size_t size)
{
- vaddr_t w2va, eva, orig_va;
+ vm_paddr_t w2va, eva, orig_va;
orig_va = va;
@@ -169,8 +171,8 @@
void
r5k_pdcache_wbinv_all_16(void)
{
- vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
- vaddr_t eva = va + mips_pdcache_size;
+ vm_paddr_t va = MIPS_PHYS_TO_KSEG0(0);
+ vm_paddr_t eva = va + mips_pdcache_size;
/*
* Since we're hitting the whole thing, we don't have to
@@ -187,8 +189,8 @@
void
r5k_pdcache_wbinv_all_32(void)
{
- vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
- vaddr_t eva = va + mips_pdcache_size;
+ vm_paddr_t va = MIPS_PHYS_TO_KSEG0(0);
+ vm_paddr_t eva = va + mips_pdcache_size;
/*
* Since we're hitting the whole thing, we don't have to
@@ -203,9 +205,9 @@
}
void
-r4600v1_pdcache_wbinv_range_32(vaddr_t va, vsize_t size)
+r4600v1_pdcache_wbinv_range_32(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line(va + size);
+ vm_paddr_t eva = round_line(va + size);
uint32_t ostatus;
/*
@@ -239,9 +241,9 @@
}
void
-r4600v2_pdcache_wbinv_range_32(vaddr_t va, vsize_t size)
+r4600v2_pdcache_wbinv_range_32(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line(va + size);
+ vm_paddr_t eva = round_line(va + size);
uint32_t ostatus;
va = trunc_line(va);
@@ -267,9 +269,9 @@
}
void
-vr4131v1_pdcache_wbinv_range_16(vaddr_t va, vsize_t size)
+vr4131v1_pdcache_wbinv_range_16(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line16(va + size);
+ vm_paddr_t eva = round_line16(va + size);
va = trunc_line16(va);
@@ -289,9 +291,9 @@
}
void
-r5k_pdcache_wbinv_range_16(vaddr_t va, vsize_t size)
+r5k_pdcache_wbinv_range_16(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line16(va + size);
+ vm_paddr_t eva = round_line16(va + size);
va = trunc_line16(va);
@@ -308,9 +310,9 @@
}
void
-r5k_pdcache_wbinv_range_32(vaddr_t va, vsize_t size)
+r5k_pdcache_wbinv_range_32(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line(va + size);
+ vm_paddr_t eva = round_line(va + size);
va = trunc_line(va);
@@ -327,9 +329,9 @@
}
void
-r5k_pdcache_wbinv_range_index_16(vaddr_t va, vsize_t size)
+r5k_pdcache_wbinv_range_index_16(vm_paddr_t va, vm_size_t size)
{
- vaddr_t w2va, eva;
+ vm_paddr_t w2va, eva;
/*
* Since we're doing Index ops, we expect to not be able
@@ -359,9 +361,9 @@
}
void
-r5k_pdcache_wbinv_range_index_32(vaddr_t va, vsize_t size)
+r5k_pdcache_wbinv_range_index_32(vm_paddr_t va, vm_size_t size)
{
- vaddr_t w2va, eva;
+ vm_paddr_t w2va, eva;
/*
* Since we're doing Index ops, we expect to not be able
@@ -391,9 +393,9 @@
}
void
-r4600v1_pdcache_inv_range_32(vaddr_t va, vsize_t size)
+r4600v1_pdcache_inv_range_32(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line(va + size);
+ vm_paddr_t eva = round_line(va + size);
uint32_t ostatus;
/*
@@ -418,9 +420,9 @@
}
void
-r4600v2_pdcache_inv_range_32(vaddr_t va, vsize_t size)
+r4600v2_pdcache_inv_range_32(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line(va + size);
+ vm_paddr_t eva = round_line(va + size);
uint32_t ostatus;
va = trunc_line(va);
@@ -449,9 +451,9 @@
}
void
-r5k_pdcache_inv_range_16(vaddr_t va, vsize_t size)
+r5k_pdcache_inv_range_16(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line16(va + size);
+ vm_paddr_t eva = round_line16(va + size);
va = trunc_line16(va);
@@ -467,9 +469,9 @@
}
void
-r5k_pdcache_inv_range_32(vaddr_t va, vsize_t size)
+r5k_pdcache_inv_range_32(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line(va + size);
+ vm_paddr_t eva = round_line(va + size);
va = trunc_line(va);
@@ -485,9 +487,9 @@
}
void
-r4600v1_pdcache_wb_range_32(vaddr_t va, vsize_t size)
+r4600v1_pdcache_wb_range_32(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line(va + size);
+ vm_paddr_t eva = round_line(va + size);
uint32_t ostatus;
/*
@@ -512,9 +514,9 @@
}
void
-r4600v2_pdcache_wb_range_32(vaddr_t va, vsize_t size)
+r4600v2_pdcache_wb_range_32(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line(va + size);
+ vm_paddr_t eva = round_line(va + size);
uint32_t ostatus;
va = trunc_line(va);
@@ -543,9 +545,9 @@
}
void
-r5k_pdcache_wb_range_16(vaddr_t va, vsize_t size)
+r5k_pdcache_wb_range_16(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line16(va + size);
+ vm_paddr_t eva = round_line16(va + size);
va = trunc_line16(va);
@@ -561,9 +563,9 @@
}
void
-r5k_pdcache_wb_range_32(vaddr_t va, vsize_t size)
+r5k_pdcache_wb_range_32(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_line(va + size);
+ vm_paddr_t eva = round_line(va + size);
va = trunc_line(va);
@@ -600,8 +602,8 @@
void
r5k_sdcache_wbinv_all(void)
{
- vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
- vaddr_t eva = va + mips_sdcache_size;
+ vm_paddr_t va = MIPS_PHYS_TO_KSEG0(0);
+ vm_paddr_t eva = va + mips_sdcache_size;
while (va < eva) {
cache_op_r4k_line(va, R5K_Page_Invalidate_S);
@@ -611,7 +613,7 @@
/* XXX: want wbinv_range_index here instead? */
void
-r5k_sdcache_wbinv_rangeall(vaddr_t va, vsize_t size)
+r5k_sdcache_wbinv_rangeall(vm_paddr_t va, vm_size_t size)
{
r5k_sdcache_wbinv_all();
}
@@ -620,9 +622,9 @@
#define trunc_page(x) ((x) & ~(128 * 32 - 1))
void
-r5k_sdcache_wbinv_range(vaddr_t va, vsize_t size)
+r5k_sdcache_wbinv_range(vm_paddr_t va, vm_size_t size)
{
- vaddr_t eva = round_page(va + size);
+ vm_paddr_t eva = round_page(va + size);
va = trunc_page(va);
while (va < eva) {
@@ -632,7 +634,7 @@
}
void
-r5k_sdcache_wb_range(vaddr_t va, vsize_t size)
+r5k_sdcache_wb_range(vm_paddr_t va, vm_size_t size)
{
/* Write-through cache, no need to WB */
}
==== //depot/projects/mips/sys/mips/mips/cache_r5k_subr.S#2 (text+ko) ====
@@ -26,10 +26,10 @@
* SUCH DAMAGE.
*/
-#include <mips/asm.h>
-#include <mips/cpuregs.h>
-#include <mips/cache_r4k.h>
-#include <mips/cache_r5k.h>
+#include <machine/asm.h>
+#include <machine/cpuregs.h>
+#include <machine/cache_r4k.h>
+#include <machine/cache_r5k.h>
.set mips3
.set noreorder
@@ -39,8 +39,8 @@
*
* Enable and clear out the R5k secondary (unified) cache.
*/
-LEAF_NOPROFILE(r5k_enable_sdcache)
- lw t2, _C_LABEL(mips_sdcache_size)
+LEAF(r5k_enable_sdcache)
+ lw t2, mips_sdcache_size
la t1, MIPS_KSEG0_START
beq t2, zero, 3f # if no sdcache, we can bail now
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