PERFORCE change 29916 for review

[Juli Mallett]

http://perforce.freebsd.org/chv.cgi?CH=29916

Change 29916 by jmallett at jmallett_dalek on 2003/04/27 19:51:03

	Add things for NetBSD compatibility.  Mostly just new
	macros and so on.  I don't like these huge headers,
	in principle, but they make life easier for now.  I've
	at least stripped out bits that don't pertain to what
	we're supporting (e.g. MIPS1 stuff is gone where I saw
	it.)

Affected files ...

.. //depot/projects/mips/sys/mips/include/cpu.h#5 edit
.. //depot/projects/mips/sys/mips/include/locore.h#1 add
.. //depot/projects/mips/sys/mips/include/mipsNN.h#1 add

Differences ...

==== //depot/projects/mips/sys/mips/include/cpu.h#5 (text+ko) ====

@@ -75,4 +75,33 @@
 	return (++now);
 }
 
+#ifndef _LOCORE
+/* XXX simonb
+ * Should the following be in a cpu_info type structure?
+ * And how many of these are per-cpu vs. per-system?  (Ie,
+ * we can assume that all cpus have the same mmu-type, but
+ * maybe not that all cpus run at the same clock speed.
+ * Some SGI's apparently support R12k and R14k in the same
+ * box.)
+ */
+extern int cpu_arch;
+extern int mips_cpu_flags;
+extern int mips_has_r4k_mmu;
+extern int mips_has_llsc;
+extern int mips3_pg_cached;
+
+#define	CPU_MIPS_R4K_MMU		0x0001
+#define	CPU_MIPS_NO_LLSC		0x0002
+#define	CPU_MIPS_CAUSE_IV		0x0004
+#define	CPU_MIPS_HAVE_SPECIAL_CCA	0x0008	/* Defaults to '3' if not set. */
+#define	CPU_MIPS_CACHED_CCA_MASK	0x0070
+#define	CPU_MIPS_CACHED_CCA_SHIFT	 4
+#define	CPU_MIPS_DOUBLE_COUNT		0x0080	/* 1 cp0 count == 2 clock cycles */
+#define	CPU_MIPS_USE_WAIT		0x0100	/* Use "wait"-based cpu_idle() */
+#define	CPU_MIPS_NO_WAIT		0x0200	/* Inverse of previous, for mips32/64 */
+#define	CPU_MIPS_D_CACHE_COHERENT	0x0400	/* D-cache is fully coherent */
+#define	CPU_MIPS_I_D_CACHE_COHERENT	0x0800	/* I-cache funcs don't need to flush the D-cache */
+#define	MIPS_NOT_SUPP			0x8000
+#endif
+
 #endif /* !_MACHINE_CPU_H_ */