PERFORCE change 29166 for review

[Marcel Moolenaar]

http://perforce.freebsd.org/chv.cgi?CH=29166

Change 29166 by marcel at marcel_nfs on 2003/04/17 18:27:01

	Implement the Data Nested TLB fault handler. This is pretty much
	a requirement now that we don't switch to physical addressing and
	don't use direct mapped virtual addressing.
	The handler obtains the PTE from the page table and performs a
	TLB insertion. The PTE has been modified first with access and
	dirty bits set to avoid Data Access and Data Dirty bit faults.
	
	The Data Nested TLB fault will fail if the kernel page tables
	are not mapped. Since we use direct mapped virtual addresses for
	them, this should not be a problem. Note however that if the
	page tables are not mapped by a translation register (but rather
	by a translation cache entry), forward progress is not guaranteed
	and we may need to be able to deal with a second nested fault.
	This has not been implemented.

Affected files ...

.. //depot/projects/ia64_epc/sys/ia64/ia64/exception.s#11 edit

Differences ...

==== //depot/projects/ia64_epc/sys/ia64/ia64/exception.s#11 (text+ko) ====

@@ -805,7 +805,64 @@
 IVT_END(Alternate_Data_TLB)
 
 IVT_ENTRY(Data_Nested_TLB, 0x1400)
-	TRAP(5)
+	// See exception_save. Things get tricky here. Don't use p14, p15,
+	// sp and r16-r21.
+{	.mlx
+	mov		r22=cr.ifa
+	movl		r24=ia64_kptdir
+	;;
+}
+{	.mmi
+	mov		r23=cr.itir
+	ld8		r24=[r24]
+	extr.u		r25=sp,PAGE_SHIFT,61-PAGE_SHIFT
+	;;
+}
+{	.mii
+	mov		cr.ifa=sp
+	shr.u		r26=r25,PAGE_SHIFT-5	// dir index
+	extr.u		r27=r25,0,PAGE_SHIFT-5	// pte index
+	;;
+}
+{	.mmi
+	shladd		r24=r26,3,r24
+	;;
+	ld8		r24=[r24]
+	shl		r27=r27,5
+	;;
+}
+{	.mmi
+	add		r24=r24,r27		// address of pte
+	;;
+	ld8		r25=[r24]
+	extr.u		r26=sp,61,3
+	;;
+}
+{	.mmi
+	mov		r26=rr[r26]
+	;;
+	or		r25=PTE_D|PTE_A,r25
+	dep		r26=0,r26,0,2
+	;;
+}
+{	.mmi
+	st8		[r24]=r25
+	mov		cr.itir=r26
+	nop		0
+	;;
+}
+{	.mmi
+	itc.d		r25
+	;;
+	srlz.d
+	nop		0
+}
+{	.mmb
+	mov		cr.ifa=r22
+	mov		cr.itir=r23
+	br.sptk		exception_save_restart
+	;;
+}
 IVT_END(Data_Nested_TLB)
 
 IVT_ENTRY(Instruction_Key_Miss, 0x1800)