USB DMA memory Allocation

[Hans Petter Selasky]

On 08/07/13 04:32, aseem.jolly wrote:
> I have gone through EHCI specification(was pretty long so couldn't finish it
> though) and below is what that I have understood.
>
> "Control Data Structure Segment Register 'CTRLDSSEGMENT', This register
> allows the host software to locate all control data structures within the
> same 4 Gigabyte memory segment. This 32-bit register corresponds to the most
> significant address bits [63:32] for all EHCI data structures.
>
> If the 64-bit Addressing Capability field in Host controller configuration
> parametere register (HCCPARAMS) is set to 1, then 'CTRLDSSEGMENT' register
> is used with the link pointers to construct 64-bit addresses to EHCI control
> data structures.
>
> This register is concatenated with the link pointer from either the
> PERIODICLISTBASE, ASYNCLISTADDR,
> or any control data structure link field to construct a 64-bit address. We
> are programming 'CTRLDSSEGMENT' to the default value(00000000h) when we
> initialize the host controller(see ehci_init function)"
>
> I believe, we have to still confine us to a 4GB range and not specifially
> [0-4GB] range. On host initialization, we can set 'CTRLDSSEGMENT' register
> to the lowest address of a particular 4GB range and then the host controller
> will be able to locate all ehci data structures with in that segment by
> concatenation. We will accordingly adjust the address boundary restrictions
> in the parent dma tag.
>
> Could you please confirm once, and let me know if I have not understood it
> correctly.
>

Yes, that is correct. Not all structures can reside anywhere in memory.

BTW: There is no such limitation for the XHCI controller.

--HPS