usb3 umass device on usb2 port not recognised
Hans Petter Selasky
hselasky at c2i.net
Fri Oct 5 06:39:12 UTC 2012
On Thursday 04 October 2012 13:43:39 Guido van Rooij wrote:
> On Thu, Oct 04, 2012 at 12:14:47PM +0200, Hans Petter Selasky wrote:
> > On Thursday 04 October 2012 10:33:44 Guido van Rooij wrote:
> > > ct 4 10:31:23 beck kernel: uhub_reattach_port: Port 3 is in Host Mode
> > > Oct 4 10:31:24 beck kernel: uhub_read_port_status: port 3,
> > > wPortStatus=0x0500, wPortChange=0x0001,
> >
> > Hi,
> >
> > There is a high speed port detection, but it somehow fails.
> > wPortChange=0x0001
> >
> > In:
> > sys/dev/usb/controller/ehci.c
> >
> > Lookup this and you find the reset sequence which is failing.
> >
> > case UHF_PORT_RESET:
> > DPRINTFN(6, "reset port %d\n", index);
> >
> > Suggestions:
> >
> > a) Do the reset sequence twice.
> > b) Reduce the USB reset delays.
>
> First of all, the uhub output was with hw.usb.ehci.no_hs=1.
> Attached the output with hw.usb.ehci.no_hs=0, and hw.usb.ehci.debug=6.
> We then see:
> Oct 4 13:24:09 beck kernel: ehci_roothub_exec: ehci after reset,
> status=0x00001802 I still see wPortStatus=0x0500, wPortChange=0x0001.
>
> status=0x00001802 means the following is set:
> 0x1000 : EHCI_PS_PP
> 0x0800 : not in ehcireg.h, but EHCI_PS_IS_LOWSPEED(..) is false
> 0x0002 : EHCI_PS_CSC
>
> because I do not see output from:
> DPRINTF("ehci port %d reset, status = 0x%08x\n",
> index, v);
> we can conclude that the following code:
> if (!(v & EHCI_PS_PE) &&
> (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
> /* Not a high speed device, give up
> ownership.*/ ehci_disown(sc, index, 0);
> break;
> }
> leads to a break. Indeed, we see:
> Oct 4 13:19:50 beck kernel: ehci_disown: index=3 lowspeed=0
>
> Yet, the device is a high speed device...
Hi,
It means that the High-speed detection failed for some reason.
Try to do like this before !(v & EHCI_PS_PE), I.E. try to do the High-Speed
reset twice.
if (!(v & EHCI_PS_PE)) {
/* Start reset sequence. */
v &= ~(EHCI_PS_PE | EHCI_PS_PR);
EOWRITE4(sc, port, v | EHCI_PS_PR);
/* Wait for reset to complete. */
usb_pause_mtx(&sc->sc_bus.bus_mtx,
USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY));
/* Terminate reset sequence. */
if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
EOWRITE4(sc, port, v);
/* Wait for HC to complete reset. */
usb_pause_mtx(&sc->sc_bus.bus_mtx,
USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
}
--HPS
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