CPU Cache and busdma usage in USB

[Hans Petter Selasky]

Hi Piotr and Rafal,

Your patch is not fully correct. It will break support for x86 and more when 
bounce pages are uses.

Let's get the definitions right:

man busdma
<cite>

             BUS_DMASYNC_PREREAD    Perform any synchronization required prior
                                    to an update of host memory by the device.

             BUS_DMASYNC_PREWRITE   Perform any synchronization required after
                                    an update of host memory by the CPU and
                                    prior to device access to host memory.

             BUS_DMASYNC_POSTREAD   Perform any synchronization required after
                                    an update of host memory by the device and
                                    prior to CPU access to host memory.

             BUS_DMASYNC_POSTWRITE  Perform any synchronization required after
                                    device access to host memory.

</cite>

My view:

XXX_PREXXX functions should be used prior to read/write device access.

In other words, PRE has to be a flush operation.

XXX_POSTXXX functions should be used after read/write device access.

In other words, POST has to be an invalidate operation.

Reading:

src/sys/arm/arm/busdma_machdep.c

I find bus_dmamap_sync_buf() to be coherent with this view.

Can you check if the COHERENT bit is set for your allocation?

        if (map->flags & DMAMAP_COHERENT)
                return;

Summed up:

The existing code is doing correct. What is known is a problem with the memory 
mapping, so that the same memory page can get mapped with different 
attributes, which makes the problem appear.

--HPS