TSC timekeeping and cpu states

[Alexander Motin]

On 14.08.2017 18:38, Ian Smith wrote:
> On Mon, 14 Aug 2017 17:16:22 +1000, Aristedes Maniatis wrote:
>  > On 14/8/17 3:08PM, Kevin Oberman wrote:
>  > > Again, the documentation lags reality. The default was changed for 
>  > > 11.0. It is still conservative. In ALMOST all cases, Cmax will yield 
>  > > the bast results. However, on large systems with many cores, Cmax 
>  > > will trigger very poor results, so the default is C2, just to be 
>  > > safe.
> 
> Given it's a server, anything beyond C2 is likely not worth trying. 
> OTOH, C2 is perhaps not worth avoiding; it's probably low latency and 
> should result in lower power consumption, so heat, and unlikely to hurt.
> 
> Or at least, I suspect that's the case .. cc'ing Alexander, as the wiki 
> article you referenced was his doing, so he's among those best placed.

C-states controlled here are ACPI C-states, which have limited relation
to real CPU C-states.  There are systems where they map exactly, but
there are also systems where ACPI C1/C2/C3 states map to CPU C1/C3/C6,
so it is difficult to make general recommendations.  Approximately the
map can be guessed looking on latency value (last of three) reported in
sysctl dev.cpu.0.cx_supported:  1 is usually CPU C1, 2+ is likely CPU
C2, 100+ can be C3, 500+ can be C6, but all that is very approximately
and I guess depends on BIOS writer mood.

What's about recommendations from me, I'd say that CPU C2 state should
not hurt in most cases, unless something is broken, but benefit is
rather small (often just covered by C1E enabled in BIOS);  CPU C3 state
gives significant power saving, but can either hurt performance due to
higher enter/exit latency or slightly improve it due to TurboBoost
activation (require CPU frequency to be set to max value); CPU C6 is
probably useful only for laptops, since it saves not so much power
power, while exit latency can be in milliseconds range.

>  > > As far as possible TSC impact, I think older processors had TSC
>  > > issues when not all cores ran with the same clock speed. That said,
>  > > I am not remotely expert on such issues, so don't take this too 
>  > > seriously.
> 
> I wasn't aware that FreeBSD could yet do different freqs on different 
> cores?  But I'm less expert than Kevin, and certainly behind the times.

On old CPUs TSC frequency was related to CPU frequency and so could
fluctuate with frequency change.  On modern CPUs it is always constant,
equal to base CPU frequency.  What's about different frequency for
different cores, IIRC ACPI allows that, but up to recent time neither
FreeBSD nor hardware could do that.  I have feeling I heard that some
very new CPUs may allow that, but to be efficient it would require very
tight interoperation between power manager and CPU scheduler, otherwise
performance may suffer.

-- 
Alexander Motin