stable/10: high load average when box is idle

[Alexander Motin]

On 26.12.2015 17:09, Ian Smith wrote:
> Current hypothesis: some variable/s are getting improperly initialised 
> at boot, but are (somehow?) getting properly re-initialised on changing 
> cpuset to 1 then back to 2 cpus - though I've no idea how, or by what.

While this is interesting hypothesis, I see no real ground for it in the
code.  My own explanation here, same as before, is in area of events
aliasing.  HPET, due to its hardware limitations, more prone to
different synchronization effects then LAPIC.  And those limitations are
specific to hardware configuration.  On modern hardware HPET may provide
(up 8) per-CPU MSI interrupts.  This is the best case for everything
with minimal chances for aliasing (unless you have more then 8 logical
cores).  On older hardware it is typical to have HPET sharing single
interrupt line with some other device(s) and generating events for all
CPUs from it.  Interrupt line sharing tends to create load of 1.0 due to
counting its own interrupt thread.  I've partially workarounded that at
some point, but aliasing possibilities are still there.  Driving
multiple CPUs from the same interrupt also creates aliasing, since
different CPUs wakeup close to each other and may count each-others
load.  Different CPU wakeup times from different sleep states and other
sources of jitter may generate quite complicated but not really useful
behavior patterns.

Happy holidays!

-- 
Alexander Motin