Makefile and '$(addprefix)' SOLVED
Andrew
andrew.chace at gmail.com
Mon May 22 16:48:26 PDT 2006
On Mon, 2006-05-22 at 18:45 -0400, Parv wrote:
> in message <1148335671.2572.10.camel at LatitudeFC5.network>,
> wrote Andrew thusly...
> >
> > I'm trying to use $(addprefix) build lists of source files and
> > object files containing the relative paths for each. The problem
> > is that $(addprefix) never seems to be evaluated. When I run 'make
> > -p', $OBJECT_LIST looks exactly like in does in my Makefile, which
> > is listed below.
> ...
> > #### Begin Makefile ####
> >
> > ## compiler settings
> > CC = gcc
> > OPTIONS = -Wall -g
> >
> > ## directory layout
> > BASEDIR = ../alice
> > SOURCEDIR = $(BASEDIR)/sources
> > OBJECTDIR = $(BASEDIR)/objects
> > DOCSDIR = $(BASEDIR)/documentation
> ...
> > SOURCES_LIST = $(addprefix, $(SOURCEDIR), $(SOURCE))
> > OBJECTS_LIST = $(addprefix, $(OBJECTDIR), $(OBJECTS))
> >
> > ## targets
> > alice: $(OBJECT_LIST)
> > $(CC) $(OPTIONS) -o $@ $(OBJECT_LIST)
> ...
>
> Looks like you are using gnu make syntax.
>
> Read make(1) man page. Replace $(VAR) with ${VAR} & see what
> happens (i am unsure as i am a light user of BSD make).
>
>
> - Parv
>
Hello all,
I've fixed my Makefile. Here's a working version, in case it will be of
help to someone else. Oh, by-the-way, this is for GNU make, not BSD
make.
-Andrew
#### Begin Makefile ####
## Makefile for GNU make
## compiler settings
CC = gcc
CFLAGS = -Wall -g
## directory layout
BASEDIR = ../alice
SRCDIR = $(BASEDIR)/sources/
OBJDIR = $(BASEDIR)/objects/
DOCDIR = $(BASEDIR)/documentation
## sources
SRC = main.c help.c status.c buffer.c device.c error.c insane.c
## objects
OBJ = main.o help.o status.o buffer.o device.o error.o insane.o
## list of objects containing relative path for each
OBJLIST = $(addprefix $(OBJDIR), $(OBJ))
## pathes for make to search
VPATH = $(SRCDIR) $(OBJDIR)
alice: $(OBJ)
$(CC) $(CFLAGS) -o $@ $(OBJLIST)
%.o: %.c alice.h
$(CC) $(CFLAGS) -c $< -o $(OBJDIR)$@
clean:
rm $(OBJLIST) *.core
distclean: clean
rm -r *~
#### End Makefile ####
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