Fatal kernel trap on 7400 G4 processors

[Nathan Whitehorn]

Marco Trillo wrote:
> Hi all,
> 
> Recent 8.0-current kernels cause a "fatal kernel trap" on 7400 G4 processors:
> 
> fatal kernel trap
> 
> exception = 0x7 (program)
> srr0 = 0x5336bc
> srr1 = 0x83032
> lr = 0x5334b4
> 
> Stopped at 0x5336bc mfspr 0, dccr
> 
> The address 0x5336bc corresponds to function cpu_setup() in powerpc/cpu.c:
> 
>   5336b4:       7f 9e 00 00     cmpw    cr7,r30,r0
>   5336b8:       40 be 02 94     bne+    cr7,53394c <cpu_setup+0x5f4>
>   5336bc:       7c 1a fa a6     mfdccr  r0 <<<<< here
>   5336c0:       3d 20 00 5f     lis     r9,95
> 
> I tracked the line to the following code in cpu.c:
> 
> 			l3cr_config = mfspr(SPR_L3CR); <<<< here
> 
> 			/* Fallthrough */
> 
> In include/spr.h I see the following:
> 
> #define	SPR_L3CR		0x3fa	/* .6. L3 Control Register */
> #define	SPR_DCCR		0x3fa	/* 4.. Data Cache Cachability Register */
> 
> So it seems that the 7400 processor doesn't have these registers so it
> causes a fault.

Apparently only the MPC745x CPUs have an L3 cache, and I just updated 
cpu.c to reflect that.

For G5 support, I wrote a piece of code that you can put in EXEC_PGM 
that writes a value to SPRG2 if a trap was taken, then tries to execute 
a 64-bit instruction to see if the CPU is 64-bit. I think we should do 
something similar to detect cache presence, Altivec support and such 
things. Since we can do this when the system is further into booting, we 
should be able to use the regular trap handlers. Is there a way to catch 
traps instead of panicing?
-Nathan