kernel stacks [eas: Re: G5 Bridge-mode MMU]

[Marcel Moolenaar]

On Apr 15, 2008, at 10:59 AM, Rafal Jaworowski wrote:
> Marcel Moolenaar wrote:
>>>> Related: how hard would it be to map the kernel above 2G and
>>>> eliminate the SR swap in the exception handlers (but do it on
>>>> context switches)?
>>>
>>> You would have to eliminate the 1:1 mapping. I know this was done in
>>> the bookE port, and it is painful to have two kernel ABIs.
>>>
>>> How about the corollary: how hard is it to get the bookE port to  
>>> use a
>>> separate address space for the kernel ?
>>
>> Probably not too hard.
>>
>> We (i.e. Juniper) discussed this with Semihalf and for Juniper the
>> single address space implementation was better, even though Semihalf
>> started with the split address space.
>
> Yeah, in the original design we considered separate address spaces,  
> but after
> discussions we went for the single AS, which apparently is simpler  
> and cheaper
> (no need for any additional temporary mappings in copyin/out,  
> exceptions and
> similar), but imposes limitations on the I/O ranges and KVA. So  
> maybe with the
> upcoming more powerful BookE systems, with lots of RAM etc. it would  
> be time
> for re-considering this, but I don't have any code from back then as  
> the idea
> died pretty quickly, before main development happened.

It would be great if we could support both -- not at runtime, but have  
it
compile-time selectable. PowerPC does cover the embedded, desktop and
server space so the needs are much more varied than for other platforms.
I don't see any immediate consequence for our user-space ABI, so it may
not be visible to user space (other than having the stack start at 4GB  
or
so)...

-- 
Marcel Moolenaar
xcllnt at mac.com