G5 Bridge-mode MMU

[Marcel Moolenaar]

On Apr 15, 2008, at 8:29 AM, Peter Grehan wrote:
> - the G5 uses two cascaded OpenPIC interrupt controllers. The  
> interrupt code needs to be reworked to support this concept.

Have the beginnings of that. Not generically enough for cascaded
OpenPICs, but close enough that I should be able to get it right
for 90% or so...

There's a bigger problem though: the current AIM pmap code and
exception handling is broken for kernel stacks. The problem is
that it is assumed by the exception code that the whole stack is
mapped and DSI traps for the stack are assumed to be stack over-
runs. If we ever need more than 1 page of kernel stack, we're
hosed. The good thing is that we now that we can safely reduce
the kernel stack to 2 pages, but the bad thing is that we need
to handle nested DSI traps or actually make sure the kernel stack
is always mapped.

Also, with process address space limited to 2G, I wonder why we
keep swapping all segment registers and not just the lower 8?
Related: how hard would it be to map the kernel above 2G and
eliminate the SR swap in the exception handlers (but do it on
context switches)?

-- 
Marcel Moolenaar
xcllnt at mac.com