G5 status

[Peter Grehan]

  I now have a 1.6GHz G5 and am attempting to get the 32-bit PPC
port running on it. There are some interesting technical challenges:

  - For processor documentation, I'm using Linux source and the IBM
"Programming Environments Manual for 64 and 32-Bit Microprocessors".
The Linux code implies that it's basically a Power4 cpu core, but I'm
not sure if it has the 16Mb 'super page' support that Power4 has.

  - The CPU is basically 64-bit, but 32-bit code should be fine since
32-bit instructions all still work, similar to MIPS64. There are a
couple of concessions: the 'bridge' mode allows the segment table
cache to act as segment registers via the mtsr/mfsr instructions,
so a segment table isn't required. However, the hashed page table
needs 64-bit entries.

  Since I'd like to have the same kernel on G4/G4/G5, there will
be some indirection needed in the pmap code to handle both forms
of page table at run-time.

  - No BAT registers! This complicates things a bit: the kernel will
have to be mapped, device addr space will be virtually mapped, and
page-zeroing will have to use the i386 temporary PTE trick, or run
in real-mode.

  The loader had some bugs that were hidden by BAT-mapping the first
256Mb of RAM.

  - There are 2 OpenPIC interrupt controllers chained together. This
will require a re-org of the interrupt code.

  - OpenFirmware uses 2 cells to describe a physical address, but only
1 for a virtual address. Another minor complication when reading memory
parameters from OFW.

  - Fan control is going to be difficult. The Linux code looks very
complicated, and I think the author had access to NDA information.
So, the port may have to run with full fans, which is *very* noisy.

later,

Peter.