[Bug 227591] [NEW PORT] devel/yosys - Verilog RTL syntensis

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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=227591

--- Comment #2 from commit-hook at freebsd.org ---
A commit references this bug:

Author: tobik
Date: Wed Jun  6 14:19:52 UTC 2018
New revision: 471844
URL: https://svnweb.freebsd.org/changeset/ports/471844

Log:
  New port: devel/yosys

  Yosys is a framework for Verilog RTL synthesis.  It currently has
  extensive Verilog-2005 support and provides a basic set of synthesis
  algorithms for various application domains.

  WWW: http://www.clifford.at/yosys/

  PR:           227591
  Submitted by: Johnny Sorocil <jsorocil at gmail.com>
  Differential Revision:        https://reviews.freebsd.org/D15632

Changes:
  head/devel/Makefile
  head/devel/yosys/
  head/devel/yosys/Makefile
  head/devel/yosys/distinfo
  head/devel/yosys/pkg-descr
  head/devel/yosys/pkg-plist

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